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參數(shù)資料
| 型號(hào)： | MM54HC299J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | WIRE |
| 中文描述： | HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20 |
| 封裝： | DIP-20 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | MM54HC299J |
AC Electrical Characteristic
(Continued) C
L
e
50 pF, t
r
e
t
f
e
6 ns unless otherwise specified
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C T
A
eb
55 to 125
§
C Units
Guaranteed Limits
Typ
t
PZH
, t
PZL
Maximum Output Enable
R
L
e
1 k
X
C
L
e
50 pF
C
L
e
150 pF
C
L
e
50 pF
C
L
e
150 pF
C
L
e
50 pF
C
L
e
150 pF
2.0V
2.0V
70
90
160
220
200
275
225
310
ns
ns
4.5V
4.5V
22
30
32
44
40
55
45
62
ns
ns
6.0V
6.0V
19
24
28
47
34
47
38
51
ns
ns
t
PHZ
, t
PLZ
Maximum Output Disable Time R
L
e
1 k
X
2.0V
4.5V
6.0V
70
22
19
160
32
28
200
40
34
225
45
38
ns
ns
ns
C
L
e
50 pF
t
S
Minimum Setup Time,
Data Select S
L
or S
R
2.0V
4.5V
6.0V
100
20
17
125
25
21
140
28
25
ns
ns
ns
t
H
Minimum Hold Time,
Data Select S
L
or S
R
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
REM
Minimum Clear Removal Time
2.0V
4.5V
6.0V
10
10
10
10
10
10
10
10
10
ns
ns
ns
t
W
Minimum Pulse Width,
Clock and Clear
2.0V
4.5V
6.0V
100
20
17
125
25
21
140
28
25
ns
ns
ns
t
r
, t
f
Maximum Input Rise
and Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
100
500
400
ns
ns
ns
t
THL
, t
TLH
Maximum Output Rise
and Fall Time, Clock
2.0V
4.5V
6.0V
60
12
10
75
15
13
90
18
15
ns
ns
ns
C
PD
Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
240
110
pF
pF
C
IN
Maximum Input Capacitance
Capacitance
5
10
10
10
pF
C
OUT
Maximum TRI-STATE
Output Capacitance
15
20
20
20
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
e
C
PD
V
CC
f
a
I
CC
.
Function Table
Inputs
Inputs/Outputs
Outputs
Function
Select
Output
Control
Mode
Clear
Clock
Serial A/Q
A
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
H/Q
H
Q
A’
SL SR
Q
H’
S1
S0
G1
2
G2
2
Clear
L
L
X
L
L
X
L
L
L
L
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Hold
H
H
L
X
L
X
L
L
L
L
X
X
X
X
X
Q
A0
Q
A0
H
L
Q
B0
Q
B0
Q
An
Q
An
Q
Cn
Q
Cn
b
Q
C0
Q
C0
Q
Bn
Q
Bn
Q
Dn
Q
Dn
c
Q
D0
Q
D0
Q
Cn
Q
Cn
Q
En
Q
En
d
Q
E0
Q
E0
Q
Dn
Q
Dn
Q
Fn
Q
Fn
e
Q
F0
Q
F0
Q
En
Q
En
Q
Gn
Q
Gn
f
Q
G0
Q
G0
Q
Fn
Q
Fn
Q
Hn
Q
Hn
g
Q
H0
Q
H0
Q
Gn
Q
Gn
H
L
Q
A0
Q
H0
Q
A0
Q
H0
H
L
L or H
u
u
u
u
u
Shift Right
H
H
L
L
H
H
L
L
L
L
X
X
H
L
Q
GN
Q
GN
H
L
Shift Left
H
H
H
H
L
L
L
L
L
L
H
L
X
X
Q
Bn
Q
Bn
a
Q
Bn
Q
Bn
a
Load
H
H
H
X
X
X
X
h
h
2
When one or both controls are high the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of
the register is not affected.
4
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