參數(shù)資料
型號： ML87V3104
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 顯示控制器
英文描述： 2048 X 1024 DOTS DOT MAT LCD DSPL CTLR, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 55/69頁
文件大小： 474K
代理商： ML87V3104
FEDL87V3104-02
OKI Semiconductor
ML87V3104
59/69
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Ta = 0 to 70°C, VDD = VDDO = VDDI = 3.3
± 0.3 V, VSS = 0 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
H level input voltage
VIH1
—
2.4
—
VDDI +0.3
V
L level input voltage
XOSCI
VIL1
—
VSS –0.3
—
0.4
V
H level input voltage
VIH
—
2.0
—
5.5
V
L level input voltage
Others
VIL
—
VSS –0.3
—
0.8
V
H level output voltage
VOH1
IOH = 8 mA
0.8VDD
—
V
L level output voltage
BSYN,
PORT0,1
VOL1
IOL = 8 mA
—
0.2VDD
V
H level output voltage
VOH2
IOH = 4 mA
0.8VDD
—
V
L level output voltage
Others
VOL2
IOL = 4 mA
—
0.2VDD
V
Input leakage current
ILI
—
–10
—
+10
A
Output leakage current
ILO
—
–10
—
+10
A
During operation
IDDI1
—
55
mA
When display is OFF
IDDI2
—
45
mA
Power supply
current
(internal core)
When not operating
IDDI3
fope = 15 MHz
—
5
mA
Clock input feedback resistance
RF
—
0.4
1.0
2.0
M
2. AC Characteristics
(Ta = 0 to 70°C, VDDO = VDDI = 3.3
± 0.3 V, VSS = 0 V)
Parameter
Symbo
l
Condition
Min.
Typ.
Max.
Unit
Operating frequency
fope
—
15.0
MHz
Output rise time (10% to 90%)
tRO
CL = 15 pF
2
—
15
ns
Output fall time (90% to 10%)
tFO
CL = 15 pF
2
—
15
ns
BCLK clock period
tCK1
—
66
—
ns
BCLK H level pulse width
tWH1
—
30
—
ns
BCLK L level pulse width
tWL1
—
30
—
ns
Input setup time (to BCLK)
tS1
—
10
—
ns
Input hold time (to BCLK)
tH1
—
8
—
ns
Output delay time (from BCLK)*1
tPD1
CL = 15 pF
5
—
20
ns
XOSCI clock period
tCK2
—
66
—
ns
XOSCI H level pulse width
tWH2
—
30
—
ns
XOSCI L level pulse width
tWL2
—
30
—
ns
Output delay time (XOSCI to CP, CPS)*1
tPD2
CL = 15 pF
2
—
25
ns
Output hold time (from CP, CPS)*2
tHCP
CL = 15 pF
25
—
50
ns
*1: The output timing characteristics are measured at the signal levels of VDD/2.
*2: The output hold time is a relative value, which should be used as a reference value for application
design.
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