參數(shù)資料
型號(hào): ML87V3104
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 顯示控制器
英文描述: 2048 X 1024 DOTS DOT MAT LCD DSPL CTLR, PQFP100
封裝: PLASTIC, TQFP-100
文件頁(yè)數(shù): 10/69頁(yè)
文件大?。?/td> 474K
代理商: ML87V3104
FEDL87V3104-02
OKI Semiconductor
ML87V3104
18/69
3.1.3 LCD AC driving signal DF
The toggle period of the DF signal (AC driving signal) can be specified to be either one frame period or the period
of the set number of lines.
Control registers:
DFFALT
[#0Dh; bit7]:
DF signal toggle mode
DFLALT
[#0Dh, #0Ch]:
(DF signal toggle period – 1), in units of a line
DFFALT
DF toggle mode
0
Reversal at one frame periods
1
Reversal at periods of (DFLALT+1) line
3.1.4 LCD data clocks CP, CPS
It is possible to select whether or not to output the CP and CPS clock pulses during the invalid period (blanking
period) of the LCD display data. In most cases, the appropriate setting is CPBLK = ‘1’ for an STN LCD and
CPBLK = ‘0’ for a TFT LCD.
Control register:
CPBLK
[#01h; bit7]:
Control of CP and CPS clock output during blanking
CPBLK
CP and CPS clock output during blanking
0
Active
1
Clock pulses are stopped
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