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參數(shù)資料
| 型號(hào)： | ML670100 |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 25 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 142K |
| 代理商： | ML670100 |
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Semiconductor
ML670100
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9
Analog-to-Digital Converter
The analog-to-digital converter is an 8-bit successive approximation analog-to-digital converter with
eight input channels and four result registers. It offers two operating mode: scan mode, which
sequentially converts the inputs from the selected set of four input channels, and select mode, which
converts the input from a single input channel.
-Resolution: 8 bits
-Eight analog input channels
-Four result registers for holding conversion results
-Operating modes
- Scan modes: Sequential conversion of the analog inputs from the upper or lower set of four
input channels
- Select mode: Conversion of the analog inputs from a single input channel
Interrupt Controller
The interrupt controller manages interrupt requests from 9 external sources and 19 internal ones and
passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. It
supports eight interrupt levels for each source for use in priority control.
-The interrupt controller supports 9 external interrupt sources connected to nEFIQ and nEIR[7:0] pins
and 19 internal interrupt sources, including the serial ports and the flexible timer channels.
-The interrupt controller simplifies interrupt priority control with a choice of eight interrupt
levels for
each source.
-The interrupt controller assigns a unique interrupt number to each source to permit
rapid branching
to the appropriate routine.
External Memory Controller
The external memory controller generates control signals for accessing external memory (ROM, SRAM,
DRAM, etc.), and other devices with address in the external memory space.
-Support for direct connection of ROM, SRAM and I/O devices
- Strobe signal outputs for a variety of memory and I/O devices
-Support for direct connection of DRAM
- Multiplexed row and column addresses
- Random access and high-speed paged modes
- Programmable wait cycle insertion
-Memory space divided into four banks
- Two banks for ROM, SRAM and I/O devices
- Two banks for DRAM
- Address space of 16 megabytes for each bank
- Separate data bus width (8 or 16 bits), wait cycle, and off time setting for each bank
-Single-stage store buffer permitting internal access during a wait cycle to external memory or device
-Arbitration of external bus requests from external devices
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