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參數(shù)資料
| 型號： | ML6694CQ |
| 英文描述： | XC95108-10TQ100C - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 100BASE - TX的物理層與5位接口 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 177K |
| 代理商： | ML6694CQ |
ML6694
3
PIN DESCRIPTION (Pin numbers for TQFP package in parentheses)
PIN
NAME
DESCRIPTION
1
(39)
AGND1
Analog ground.
2-6
(40-44)
TSM<4:0>
Transmit data TTL inputs. TSM<4:0> inputs accept TX data symbols. Data
appearing at TSM<4:0> are clocked into the ML6694 on the rising edge of TXC.
7
(1)
PWRDN
Device power down input. A low signal powers down all ciruits of the ML6694, and
dissipates less than 20mA.
8,9,
(2, 3,
RSM<4:0>
Receive data TTL outputs. RSM<4:0> outputs may be sampled synchronously with
11,13, 5, 7, 9)
RXC’s rising edge.
15
10
(4)
DGND1
Digital ground.
12
(6)
DVCC1
Digital +5V power supply.
14
(8)
DGND2
Digital ground.
16
(10)
RXC
Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned
with the internal 125MHz bit clock recovered from the signal received at TPINP/N
when data is present. Receive data at RSM<4:0> change on the falling edges and
should be sampled on the rising edges of this clock. RXC is phase aligned to TXC
when 100BASE-TX signal is not present at TPINP/N
17
(11)
DGND3
Digital ground.
18
(12)
DVCC2
Digital +5V power supply.
19
(13)
DGND4A
Digital ground.
20
(14)
DGND4B
Digital ground.
21
(15)
DGND4C
Digital ground.
22
(16)
DVCC5
Digital +5V power supply.
23
(17)
DGND5
Digital ground.
24
(18)
SD0
Signal detect TTL output. A high output level indicates 100BASE-TX activity at
TPINP/N with an amplitude exceeding the preset threshold. The signal detect
function is active only in 100Mbps mode, that is when the pin SEL10/
100 is low.
25
(19)
SEL10/
100
Speed select TTL input. Driving this pin high disables 100BASE-TX transmit and
receive functions, and enables the 10BASE-T transmit path from 10BTTXINP/N to
TPOUTP/N. A low signal on SEL10/
100 disables the 10BTTXINP/N inputs and enables
100BASE-TX operation.
28
(22)
AVCC3
Analog positive power supply.
30
(24)
RGMSET
Equalizer bias resistor input. An external 9.53k
, 1% resistor connected between
RGMSET and AGND3 sets internal time constants controlling the receive equalizer
transfer function.
31
(25)
RTSET
Transmit level bias resistor input. An external 2.49k
, 1% resistor connected
between RTSET and AGND3 sets a precision constant bias current for the twisted
pair transmit level.
32
(26)
AGND3
Analog ground.
33,34 (27,28)
TPOUTN/P
Transmit twisted pair outputs. This differential current output pair drives MLT-3
waveforms into the network coupling transformer in 100BASE-TX mode, and
10BASE-T or FLP waveforms in 10BASE-T mode.
35
(29)
AGND2
Analog ground.
36
(30)
AVCC2
Analog +5V power supply.
37,38 (31, 32)
TPINN/P
Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals
from the network.
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PDF描述 |
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| ML6695CQ | 100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML925J40F-11 | 1610 nm, LASER DIODE |
| MLF0805-082M | 1 ELEMENT, 0.082 uH, FERRITE-CORE, GENERAL PURPOSE INDUCTOR, SMD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6695 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML6695CQ | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML6696 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer |
| ML6696CH | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer |
| ML6696CQ | 制造商:Micro Linear 功能描述:DATACOM, INTERFACE CIRCUIT, PQCC52 |
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