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參數(shù)資料
| 型號(hào)： | ML6692CH |
| 英文描述： | 100BASE-TX Physical Layer with MII |
| 中文描述： | 100BASE - TX的物理層與信息產(chǎn)業(yè)部 |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | ML6692CH |
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April 1999
ML6692
100BASE-TX Physical Layer with MII
1
GENERAL DESCRIPTION
The ML6692 implements the complete physical layer of
the Fast Ethernet 100BASE-TX standard. The ML6692
interfaces to the controller through the standard-compliant
Media Independent Interface (MII). The ML6692
functionality includes auto-negotiation, 4B/5B encoding/
decoding, Stream Cipher scrambling/descrambling,
125MHz clock recovery/generation, receive adaptive
equalization, baseline wander correction, and MLT-3/
10BASE-T transmitter.
For applications requiring 100Mbps only, such as
repeaters, the ML6692 offers a single-chip per-port
solution. For 10/100 dual speed adapters or switchers,
10BASE-T functionality may be attained using Micro
Linear’s ML2653, or by using an Ethernet controller that
contains an integrated 10BASE-T PHY.
BLOCK DIAGRAM (PLCC Package)
FEATURES
s
Single-chip 100BASE-TX physical layer
s
Compliant to IEEE 802.3u 100BASE-TX standard
s
Supports adapter, repeater and switch applications
s
Single-jack 10BASE-T/100BASE-TX solution when used
with external 10Mbps PHY
s
Compliant MII (Media Independant Interface)
s
Auto-negotiation capability
s
4B/5B encoder/decoder
s
Stream Cipher scrambler/descrambler
s
125MHz clock recovery/generation
s
Baseline wander correction
s
Adaptive equalization and MLT-3 encoding/decoding
s
Supports full-duplex operation
1
TXCLKIN
9
TXCLK
3
TXD3
4
TXD2
5
TXD1
6
TXD0
7
TXEN
8
TXER
40
39
TPOUTP
TPOUTN
PCS TRANSMIT
STATE MACHINE
NRZ TO NRZI ENCODER
SERIALIZER
MLT-3 ENCODER
EQUALIZER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
CLOCK AND DATA
RECOVERY
NRZI TO NRZ DECODER
DESERIALIZER
FLP/100BASE-TX/10BASE-T
TWISTED PAIR DRIVER
CARRIER AND
COLLISION LOGIC
MII MANAGEMENT
REGISTERS
AUTO-NEGOTIATION
AND CONTROL LOGIC
INITIALIZATION
REGISTER
37
RTSET
45
TPINP
49
48
10BTTXINN
44
TPINN
46
36
RGMSET
43
CMREF
LINK100
18
CRS
19
COL
17
RXCLK
10
RXD3
12
RXD2
14
RXD1
16
RXD0
21
RXDV
23
RXER
24
MDC
25
MDIO
10BTTXINP
33
35
SEL100T4 /EDOUT
SEL10FD /ECLK
31
32
SEL10HD
EDIN
50
51
10BTLNKEN
10BTRCV
47
DUPLEX
29
30
T4FAIL
T4EN
CLOCK SYNTHESIZER
PCS RECEIVE
STATE MACHINE
5B/4B DECODER
DESCRAMBLER
4B/5B ENCODER
SCRAMBLER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML6692CQ | 100BASE-TX Physical Layer with MII |
| ML6694CH | 100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | XC95108-10TQ100C - NOT RECOMMENDED for NEW DESIGN |
| ML6695CQ | 100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML925J40F-11 | 1610 nm, LASER DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6692CQ | 制造商:MICRO-LINEAR 制造商全稱(chēng):MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with MII |
| ML6694 | 制造商:MICRO-LINEAR 制造商全稱(chēng):MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CH | 制造商:MICRO-LINEAR 制造商全稱(chēng):MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | 制造商:MICRO-LINEAR 制造商全稱(chēng):MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6695 | 制造商:MICRO-LINEAR 制造商全稱(chēng):MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
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