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ML6652
5
January 2002
Preliminary Datasheet
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
6
AD10
I
Sets the value of the PHY address bits 1 and 0 for accessing the Serial
Management Interface.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
7
PECLTP
I
The copper interface is selected as shown in Table 2. When twisted pair
interface is selected, the scrambler and descrambler are enabled by default
and can be disabled with a management register bit.
When using twisted pair interface, this pin also defines the maximum
supported link distance. When the 10 meters maximum link length is selected,
the input is not equalized before being sliced.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
e
m
a
N
n
i
PW
I
L
4
D
A2
3
D
A0
1
D
A
l
e
v
e
L
t
u
p
n
In
o
i
t
c
n
u
F
W
I
Lt
i
B
4
D
A
Y
H
Pt
i
B
3
D
A
Y
H
Pt
i
B
2
D
A
Y
H
Pt
i
B
1
D
A
Y
H
Pt
i
B
0
D
A
Y
H
P
0d
e
l
b
a
s
i
D0
0
C
V
f
o
3
/
1d
e
l
b
a
n
E0
1
0
1
0
C
V
f
o
3
/
2d
e
l
b
a
n
E1
1
C
Vd
e
l
b
a
s
i
D1
0
1
0
1
Table 1.
P
T
L
C
E
P
t
a
s
e
c
a
f
r
e
t
n
I
d
n
a
N
I
P
T
/
P
N
I
P
T
N
T
U
O
P
T
/
P
T
U
O
P
T
P
T
L
C
E
P
>
3
.
0
3
<
t
l
u
a
f
e
D
h
t
g
n
e
L
r
e
p
o
C
P
T
R
O
H
S
>
2
.
0
3
<
t
l
u
a
f
e
D
t
n
e
r
u
C
t
u
p
t
u
O
T
U
O
P
T
I
W
O
L
>
4
.
0
3
<
t
l
u
a
f
e
D
0r
i
a
P
d
e
t
s
i
w
T0
X
T
-
e
s
a
B
0
1
d
r
a
d
n
a
t
S
0d
r
a
d
n
a
t
S0
C
V
f
o
3
/
1L
C
E
P
V
L
/
L
C
E
P1
s
e
c
a
r
T
B
C
P0
A
N0
C
V
f
o
3
/
2r
i
a
P
d
e
t
s
i
w
T0
s
e
c
a
r
T
B
C
P1
w
o
L1
C
Vr
i
a
P
d
e
t
s
i
w
T0
m
0
11
d
r
a
d
n
a
t
S0
Table 2.