參數(shù)資料
型號(hào)： ML60851CGA
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù)： 55/67頁
文件大?。?/td> 389K
代理商： ML60851CGA
ML60851C
Semiconductor
59/67
PEDL60851C-02
DMA Transfer Timing (8)
Memory to ML60851C (Demand Transfer, Dual Address Mode)
Parameter
Symbol
Condition
Note
DREQ Disable Time
t1
t2
CS Hold Time
Write Data Setup Time
t4
Unit
ns
Max.
Min.
—20
Write Data Hold Time
t5
ns
FIFO Access Time
t3
ns
Recovery Time
t6
ns
Load 20 pF
8-bit DMA
16-bit DMA
—
0
30
2
42
63
105
1
2
3
FIFO WRITE
Notes: 1. When in Dual Address mode, the DACK is ignored.
A7:A0 specifies the FIFO address.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
t2 is defined depending on CS or WR which becomes active last.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
t1
t3
t2
t4
Last Packet Write
A7:A0
DREQ
CS
WR
DIN
t5
t6
(Note) Refer to the previous page.
(Note)
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