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參數(shù)資料
| 型號(hào)： | ML54051 |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120 |
| 文件頁數(shù)： | 37/37頁 |
| 文件大小： | 304K |
| 代理商： | ML54051 |
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Semiconductor
ML54051
5/33
3.3 External SRAM Interface
Signal Name
ra [16:0]
Type
O
Pin Count
17
Description
Address bus for external SRAM
Total 28 pins
rd [7:0]
B
8
Data bus for external SRAM
rren
O
1
Read enable signal for external SRAM
rwen
O
1
Write enable signal for external SRAM
rcen
O
1
Chip enable signal for external SRAM
3.4 Extended Bus Interface
The extended bus interface is a signal line for the ML54051’s internal microcontroller. The
extended bus interface is used for purposes such as debugging.
Signal Name
xah [15:8]
Type
B
Pin Count
8
Description
Address bus for extended bus
Total 19 pins
xad [7:0]
B
8
Address/data bus for extended bus
xrd
B
1
Read signal for extended bus
xwr
B
1
Write signal for extended bus
xale
B
1
Address latch enable signal for extended bus
xpsen
I
(1)
Program store enable signal for extended bus
xint
O
(1)
Interrupt signal for extended bus
xrst
O
(1)
Reset signal for extended bus
xclk
O
(1)
Clock signal for extended bus
*
In an external ROM connection mode, xah, xad, xrd, xwr, and xale are used to connect to
external ROM.
3.5 Other Interfaces
Signal Name
txd/pcfg [0]
Type
B
Pin Count
1
Description
Serial data I/O and chip mode setting
Total 5 pins
rxd/pcfg [1]
I
1
porn
I
1
Power-on-reset signal (connect to power monitor circuit)
xin
I
1
Clock I/O (connect a crystal oscillator between xin and xout)
xout
O
1
*
The chip mode is determined depending upon the status of pcfg[1:0] when the porn signal
rises.
pcfg[1:0] = 11 : Normal mode
pcfg[1:0] = 01 : External CPU connection mode
pcfg[1:0] = 10 : External ROM connection mode
pcfg[1:0] = 00 : Test mode (normally not used)
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