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參數(shù)資料
| 型號： | ML54051 |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120 |
| 文件頁數(shù)： | 19/37頁 |
| 文件大小： | 304K |
| 代理商： | ML54051 |
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Semiconductor
ML54051
22/33
6.6.9
Status Register & Alternate Status Register (Read Only)
This register indicates the internal status of the controller. When the host reads this register, the
controller clears pending interrupt requests. However, even if the alternate status register is
read, interrupts requests will not be cleared.
D7
BUSY
D6
RDY
D5
DWF
D4
DSC
D3
DRQ
D2
CORR
D1
IDX
D0
ERR
BUSY:
This bit is set in the following cases:
from the time when the host writes a command to the command register
until processing of the command is completed
when hardware and software resets have been executed from the host
RDY:
This bit indicates Drive Ready.
DWF:
This bit is set when an error related to substitute processing occurs during
access to the internal flash memory. If this bit is set, commands that follow
may not execute properly.
DSC:
This bit is always set to 1.
DRQ:
During execution of a command that involves data transfer, this bit is set once
the transfer preparations are made.
CORR:
This bit indicates that a correctable error has occurred during access to flash
memory.
IDX:
This bit is always set to 0.
ERR:
This bit is set when an error occurs during command execution. Detailed
information is set in the error register.
6.6.10 Device Control Register (Write Only)
This register is used to control interrupt requests from the card and to specify software reset.
D7
D6
D5
X
D4
D3
1
D2
SRST
D1
-IEN
D0
0
SRST:
While this bit is 1, the controller is in the reset state.
-IEN:
1: Interrupt signal mask, 0: Interrupt signal non-mask
6.6.11
Command Register (Write Only)
This register is used to set the command code.
D7
D6
D5
D4
Command Code
D3
D2
D1
D0
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