參數(shù)資料
型號(hào)： MK51X256CMC100R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁(yè)數(shù)： 37/70頁(yè)
文件大?。?/td> 1827K
代理商： MK51X256CMC100R
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
CMRR
Common mode
rejection ratio
Gain=1
Gain=64
TBD
—
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
VOFS
Input offset
voltage
—
0.2
TBD
mV
Gain=1, ADC
Averaging=32
TGSW
Gain switching
settling time
—
10
s
dG/dT
Gain drift over
temperature
Gain=1
Gain=64
—
TBD
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
—
TBD
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
Gain=1
Gain=64
—
TBD
%/V
VDDA from 1.71
to 3.6V
EIL
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
differential input
signal swing
where VX = VREFPGA × 0.583
V
SNR
Signal-to-noise
ratio
Gain=1
Gain=64
TBD
83.0
57.5
—
dB
16-bit
differential
mode,
Average=32
THD
Total harmonic
distortion
Gain=1
Gain=64
TBD
89.4
90.0
—
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
SFDR
Spurious free
dynamic range
Gain=1
Gain=64
TBD
90.9
77.0
—
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
Table continues on the next page...
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
42
Preliminary
Freescale Semiconductor, Inc.
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