參數(shù)資料
型號(hào)： MK51X256CMC100R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁數(shù)： 26/70頁
文件大小： 1827K
代理商： MK51X256CMC100R
Table 19. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
teewr16bers Word-write to erased FlexRAM location
execution time
—
100
TBD
μs
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
Word-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
—
TBD
1.5
TBD
2.5
ms
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
200
TBD
μs
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
Longword-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
—
TBD
2.7
TBD
3.7
ms
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
Description
Typ.
Unit
IDD_PGM
Worst case programming current in program flash
10
mA
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
TBD
—
years
tnvmretp1k Data retention after up to 1 K cycles
10
TBD
—
years
tnvmretp100 Data retention after up to 100 cycles
15
TBD
—
years
nnvmcycp
Cycling endurance
10 K
TBD
—
cycles
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
TBD
—
years
Table continues on the next page...
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
32
Preliminary
Freescale Semiconductor, Inc.
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