參數資料
型號： MK51DN512ZCMD10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝： 13 X 13 MM, MAPBGA-144
文件頁數： 14/77頁
文件大?。?/td> 1066K
代理商： MK51DN512ZCMD10
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock
—
25
MHz
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
External reset pulse width (digital glitch filter disabled)
100
—
ns
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time (high drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
—
12
TBD
36
TBD
ns
Port rise and fall time (low drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
—
32
TBD
36
TBD
ns
1. The greater synchronous and asynchronous timing must be met.
General
K51 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
21
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