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參數(shù)資料
| 型號： | MK50X256CMC100 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121 |
| 封裝： | 8 X 8 MM, MAPBGA-121 |
| 文件頁數(shù)： | 46/69頁 |
| 文件大小： | 1770K |
| 代理商： | MK50X256CMC100 |
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Table 31. Op-amp electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IBIAS
Input bias current (0~105°C)
—
TBD
—
pA
VCML
Input common mode voltage low
0
—
V
VCMH
Input common mode voltage high
—
VDD
V
RIN
Input resistance
500
—
MΩ
CIN
Input capacitance
—
TBD
pF
|XIN|
AC input impedance (fIN=100kHz)
—
50
—
MΩ
CMRR
Input common mode rejection ratio
60
—
dB
PSRR
Power supply rejection ratio
60
—
dB
SR
Slew rate (
ΔVIN=100mV), low-power mode
0.1
—
V/μs
SR
Slew rate (
ΔVIN=100mV), high-speed mode
1
—
V/μs
GBW
Unity gain bandwidth, low-power mode
0.15
—
MHz
GBW
Unity gain bandwidth, high-speed mode
1
—
MHz
AV
DC open-loop voltage gain
80
90
—
dB
CL(max)
Load capacitance driving capability
—
TBD
pF
ROUT
Output resistance
—
TBD
Ω
VOUT
Output voltage range
0.1
—
TBD
V
IOUT
Output load current
—
±0.5
—
mA
GM
Gain margin
—
20
—
dB
PM
Phase margin
45
56
—
deg
Tsettle
Settling time (Buffer mode, low-power mode)
(To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k)
—
TBD
—
μs
Tsettle
Settling time (Buffer mode, high-speed mode)
(To<0.1%, Vin=2Vp-p, CL=25pF, RL=100k)
—
TBD
—
μs
Vn
Voltage noise density (noise floor) 1kHz
—
350
TBD
nV/√Hz
Vn
Voltage noise density (noise floor) 10kHz
—
90
TBD
nV/√Hz
6.6.5 Transimpedance amplifier electrical specifications — full range
Table 32. TRIAMP full range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VIN
Input voltage range
-0.2
VDDA-1.4
V
CL
Output load capacitance
100
pf
ROUT
Output resistance
1500
Ω
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
50
Preliminary
Freescale Semiconductor, Inc.
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