參數(shù)資料
型號(hào): MK2049-45SILFTR
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 125 MHz, OTHER CLOCK GENERATOR, PDSO20
封裝: 0.300 INCH, LEAD FREE, SOIC-20
文件頁數(shù): 8/9頁
文件大?。?/td> 185K
代理商: MK2049-45SILFTR
3.3V Communications Clock PLL
MDS 2049-45 G
8
Revision 101904
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2049-45
Note 1: Minimum high or low time of input clock.
Note 2: For the 1.544 MHz and 2.048 MHz output selections, the input to output clock skew is not
controlled nor predictable and will change between power up cycles. Because it is dependent on the phase
relationship between the output and feedback divider states following power up, the input to output clock
skew will remain stable during a given power up cycle. If controlled input to output skew is desired for this
output clock frequency please refer to the MK2049 or MK2069 products.
Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode
(SEL2:0 = 100, 19.44 MHz external crystal).
Marking Diagram
Marking Diagram (Pb free)
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week
that the part was assembled.
3. “LF” designates Pb (lead) free package.
Timing Jitter, Filtered
65kHz-1.3MHz (OC-3)
tjf
Referenced to
Mitel/Zarlink MT9045,
Note 3
230
ps
Frequency Error
Relative to ICLK
0
ppm
Nominal Output Impedance
ZOUT
20
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
1
10
11
20
MK2049-45SI
######
YYWW
1
10
11
20
MK2049-45SILF
######
YYWW
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