- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄65811 > MK2049-45SILFTR 125 MHz, OTHER CLOCK GENERATOR, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | MK2049-45SILFTR |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, LEAD FREE, SOIC-20 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 185K |
| 代理商： | MK2049-45SILFTR |
3.3V Communications Clock PLL
MDS 2049-45 G
4
Revision 101904
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2049-45
the MK2049-45 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK2049-45 is configured to generate a set of
output frequencies from an 8 kHz input clock. Please
refer to the Output Clock Selection Table on Page 2.
Input bits FS3:0 are set according to this table, as is the
external crystal frequency. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK2049-45. Failure to do so may result in
reduced frequency pullability range, inability of the loop
to lock, or excessive output phase jitter.
The MK2049-45 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK2049-45 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the MK2049-45 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2049-45 and the
crystal.
To obtain a list of qualified crystal devices please visit
our website at:
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The MK2049-45 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on
this page, the external loop filter is made up of
components RS, CS and CP. RSET establishes PLL
charge pump current and therefore influences loop
filter characteristics.
Tools for optimizing the values of these four
components can be found at:
CAP2
CAP1
0.0003 F
820 kohms
0.1 F
Figure 3. Typical Loop Filter
R
S
C
P
C
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2475-24SLFT | 60 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2475-24ST | 60 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2703BS | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK2703BSI | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK2703BSILFTR | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-45SITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK205/100G | 制造商:Fischer Elektronik GmbH & Co KG 功能描述:Bulk |
| MK2058-01 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Communications Clock Jitter Attenuator |
| MK205801SI | 制造商:ICS 功能描述: |
| MK2058-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。