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參數(shù)資料
| 型號(hào)： | MK2049-44SI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MK2049-44SI |
MK2049-44
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
IDT / ICS 3.3 VOLT COMMUNICATIONS CLOCK PLL
4
MK2049-44
REV A 050203
Application Information
Output Frequency Configuration
The MK2049-44 is configured to generate a set of output
frequencies from an 8 kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits FS3:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2049-44. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2049-44 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2049-44 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2049-44 are designed
to have zero frequency when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should use
short traces between the MK2049-44 and the crystal.
A complete description of the recommended crystal
parameters in the ICS application note, MAN05.
To obtain a list of qualified crystal devices please visit our
website at:
http://www.icst.com/products/telecom/vcxocrystals.htmor
email telecom@icst.com
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2049-44 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components RS,
CS and CP. RSET establishes PLL charge pump current and
therefore influences loop filter characteristics.
A “normalized” PLL loop bandwidth may be calculated as
follows:
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
CAP2
CAP1
5.6nF
750 k
0.56
F
Figure 3. Typical Loop Filter
R
Z
C2
C1
NBW
R
S
I
CP
×
575
×
N
----------------------------------------
=
Damping Factor
R
S
625
I
CP
×
C
S
×
N
------------------------------------------
×
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-45 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3V Communications Clock PLL |
| MK2049-45ASI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-45ASILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-45ASILFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-45ASITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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