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參數(shù)資料
| 型號： | MK1581-01GITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 152K |
| 代理商： | MK1581-01GITR |
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
5
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK1581-01
A “normalized” PLL loop bandwidth may be calculated
as follows:
The “normalized” bandwidth (NBW) equation above
does not take into account the effects of damping factor
or the second pole. NBW is approximately equal to the
actual -3dB bandwidth of the loop when the damping
factor is about 5 and C2 is very small. In most
applications, NBW is about 75% of the actual -3dB
bandwidth. However, NBW does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
CS = Value of capacitor CS in loop filter
(Farads)
As a general rule, the following relationship should be
maintained between components CS and CP in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
components CS and CP.
These recommendations can be found in the design
aid tools section of www.icst.com.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
W trace (a
commonly used trace impedance), place a 33
W resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
W. (The optional series termination resistor
is not shown in the External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK1581-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK1581-01 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection
for Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
RSET
Charge Pump Current
(ICP)
1.4 M
W
10
mA
680 k
W
20
mA
540 k
W
25
mA
120 k
W
100
mA
NBW
RS ICP
575
N
---------------------------------------
=
Damping Factor
RS
625
I
CP
CS
N
-----------------------------------------
=
CP
CS
20
------
=
C onnection to 3.3V
Pow er Plane
Ferrite
Bead
B ulk D ecoupling C apac itor
(such as 1
F Tantalum)
V DD P in
0.01
F Decoupling Capacitors
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