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參數(shù)資料
| 型號(hào)： | MK1581-01GITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | MK1581-01GITR |
MK1581-01
MDS 1581-01 C
1
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
Low Phase Noise T1 / E1 Clock Generator
Description
The MK1581-01 provides synchronization and timing
control for T1 and E1 based network access or
multitrunk telecommunication systems. The device
accepts an 8 kHz frame clock input and uses an
on-chip VCXO to produce a synchronized low phase
noise clock output.
This monolithic IC, combined with an external
inexpensive quartz crystal, can be used to replace a
more costly hybrid VCXO retiming module. Through
selection of external loop filter components values, the
device can be tailored to meet the system’s clock jitter
attenuation requirements. Low-pass jitter attenuation
characteristics in the Hz range are possible.
Features
Generates a T1 (1.544 MHz) or E1 (2.048 MHz)
output clock from an 8kHz frame clock input
Configurable jitter attenuation characteristics,
excellent for use as a Stratum source de-jitter circuit
VCXO-based clock generation ensures very low jitter
and phase noise generation
Output clock is phase and frequency locked to the
input reference clock
+115ppm minimum crystal frequency pullability
range, using recommended crystal
Industrial temperature range
Low power CMOS technology
16 pin TSSOP package
Single 3.3V power supply
Block Diagram
Charge
Pump
VCXO
Pullable Crystal
Output
Divider
Feedback
Divider
8kHz_IN
CLK
X2
X1
ISET
VDD
3
VDD
VIN
CHGP
5
GND
SEL
Phase
Detector
C
P
C
S
R
S
R
SET
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