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參數(shù)資料
| 型號： | MK1573-02S |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 60.41957 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 84K |
| 代理商： | MK1573-02S |
MK1573-02
GenClock HSYNC to Video Clock
MDS 1573-02 B
4
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800telwww.icst.com
The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefor a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The values
of the RC network determine the bandwidth of the PLL.
The tracking of the jitter on the HSYNC input improves with increasing values of R and decreasing values of
C, until a point is reached where the loop starts becoming unstable. At that point, HSYNC tracking becomes
unreliable. Loop filter values between 470pF and 0.01F, and 18k
and 120k will work for most
application where the PLL must track HSYNC jitter with minimum error. A good starting point is 680pF
and 82k
. The optimum values should be determined by the spectral characteristics of the HSYNC jitter.
The following formula gives the approximate loop bandwidth for the MK1573:
where:
fbw is the loop bandwidth in Hertz
fclk1 is the frequency of CLK1 in Hertz
C is the value of capacitor in Farads
For example, if CLK1 is running at 24MHz and C=1000pF, then
fbw =
fclk1 C
537
fbw =
537
24x106 1x10-9
= 3.47kHz
Loop Bandwidth and Loop Filter Component Selection
Video Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1573-02 ROM, which shows that the
accuracies are within one ppm for the output clocks.
PC Board Layout
A proper board layout is critical to the successful
use of the MK1573. In particular, the CAP1 and
CAP2 pins are very sensitive to noise and leakage
(CAP1 at pin 4 is the most sensitive). Traces
must be as short as possible and the capacitor
and resistor must be mounted next to the device
as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply
decoupling capacitor.
The high frequency output clocks on CLK1 and
CLK2 may benefit from a series 33
resistor
connected close to the pin (not shown).
1
2
3
4
5
6
7
8
G
V
=connect to VDD
=connect to GND
V
G
16
15
14
13
12
11
10
9
cap
If minimum absolute jitter is required, the RC network should be replaced by a single capacitor with a value
between 0.01F and 2F. Larger values will cause the PLL to start more slowly. For example, if C=2F, the
loop may take several seconds to start.
cap
resist.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1573-02STR | 制造商:ICS 制造商全稱:ICS 功能描述:GenClock⑩ HSYNC to Video Clock |
| MK1574 | 制造商:ICS 制造商全稱:ICS 功能描述:Frame Rate Communications PLL |
| MK1574-01AS | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MK1574-01ASI | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1574-01ASITR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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