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參數(shù)資料
| 型號： | MK1573-02S |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 60.41957 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 84K |
| 代理商： | MK1573-02S |
MK1573-02
GenClock HSYNC to Video Clock
MDS 1573-02 B
3
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800telwww.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
250
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
4.5
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage
IOH=-4mA
VDD-0.4
V
Output High Voltage
IOH=-25mA
2.4
V
Output Low Voltage
IOL=25mA
0.4
V
Operating Supply Current, IDD
No Load, VDD=5.0V
15
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
7
pF
Actual mean frequency error versus target, note 2
Any clock selection
0
1
ppm
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency, NTSC
15.734264
kHz
Input Frequency, PAL
15.625
kHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, High Time
At VDD/2
40
49 to 51
60
%
Absolute Clock Period Jitter
TBD
ps
Output Enable Time, OE high to outputs on
50
ns
Output Disable Time, OE low to tri-state
3
s
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Most selections have zero ppm error. Some selections have a maximum of 1 ppm synthesis error .
External Components/Crystal Selection
Electrical Specifications
The MK1573 requires a minimum number of external components for proper operation. A 0.1F low
leakage capacitor (see Capacitor Selection on following page) should be connected between CAP1 and
CAP2 as close to the chip as possible. A high quality ceramic capacitor is recommended. A decoupling
capacitor of 0.1F must be connected between VDD and GND pins (pins 2 and 3, 5 and 7) close to the
chip, and 33
terminating resistors can be used on clock outputs with traces longer than 1 inch.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK1573-02STR | 制造商:ICS 制造商全稱:ICS 功能描述:GenClock⑩ HSYNC to Video Clock |
| MK1574 | 制造商:ICS 制造商全稱:ICS 功能描述:Frame Rate Communications PLL |
| MK1574-01AS | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MK1574-01ASI | 功能描述:時鐘發(fā)生器及支持產品 FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1574-01ASITR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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