- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄65810 > MK1492-03RLF 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 PDF資料下載
參數(shù)資料
| 型號(hào)： | MK1492-03RLF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, SSOP-28 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 70K |
| 代理商： | MK1492-03RLF |
MK1492-03
Intel Mobile/SDRAM Clock Source
MDS 1492-03 D
4
Revision 020298
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
I C R O
C LOC K
Power-On Default Conditions
Input Pin#
Function
Default Condition
5
OE
M
All outputs enabled.
15
CPUS#
1
HOST clocks running.
16
PCISTP#
1
PCI clocks running.
19
DS
1
HOST7, HOST8 disabled.
21
SEL0
1
48/24 (pin 21) set to 48 MHz
22
LE
1
Low EMI function OFF
24
FS
1
HOST frequency = 66.66 MHz.
25
SEL1
M
F1 (pin 28) set to 27 MHz
27
CSSS
1
Allows CPU STOP mode. Refer to Power Down Control Table on page 2.
28
PEN
M
PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
General I 2C Serial Interface Operation
A. The I2C address for the MK1492-03 is D2(hex). For the clock generator to be addressed by an I2C
controller, this address must be sent as a start sequence, with an acknowledge bit between each byte as
shown below.
MK1492-03 Address (7 bits)
+ R/W# bit
8 bits dummy
ACK
Command code
ACK
Byte count
ACK
D2(hex)
Then Bytes 0, 1, 2, 3, 4, 5
in sequence unless a STOP
condition is encountered.
B. The MK1492-03 is an I2C slave component only. It does not have any read-back capability.
C. The data transfer rate supported by the MK1492-03 is 100K bits/sec (standard mode).
D. The input is operating at 3.3 V logic levels (refer to Electrical Specifications Table).
E. The data byte format is 8-bit bytes.
F. To simplify the I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent,
but the data is ignored for those two bytes. The data is loaded until a Stop condition is encountered.
G. In the power down mode (CPUS# Low), the SDATA and SCLK pins are tristated and the internal data
latches maintain all prior programming information.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for its default condition;
Bytes 1 through 5 default to a 1 (Enabled output state).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK1492-03RTR | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| MK1581-01GILF | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK1581-01GITR | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK1581-01GI | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK1704A | 140 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1492-03RTR | 功能描述:IC CLK SRC MOBILE/SDRAM 28-QSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| MK1493-01 | 制造商:ICS 制造商全稱:ICS 功能描述:PCI Clock Generator |
| MK1493-01G | 制造商:ICS 制造商全稱:ICS 功能描述:PCI Clock Generator |
| MK1493-01GTR | 制造商:ICS 制造商全稱:ICS 功能描述:PCI Clock Generator |
| MK1493-03B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PCI CLOCK GENERATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。