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參數(shù)資料
| 型號(hào)： | MK1479S |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 71.5 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 43K |
| 代理商： | MK1479S |
MK1479
Digital 21230 Video Codec Clock
MDS1479GC
3
Revision 2108
Printed 2/10/98
MicroClock division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.5
5.5
V
Operating Voltage, VDDP
3.0
3.3
5.5
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
65
mA
Short Circuit Current
Each output
±100
mA
Frequency synthesis error
All clocks
0
ppm
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
27.00000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
300
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The MK1479 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND, as close to the MK1479 as possible. A
series termination resistor of 33
may be used for each clock output.The 27.000 MHz crystal must be
connected as close to the chip as possible. The 27.000 MHz crystal should be a parallel mode, fundamental
cut. External capacitors from each of the X1 and X2 pins to ground should be added with a value in pF
equal to (CL-10.5)2, where CL is the crystal load capacitance in pF. So for a crystal with load capacitance
of 18pF, 15pF capacitors should be used.
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