參數(shù)資料
型號(hào): MK1479S
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 71.5 MHz, VIDEO CLOCK GENERATOR, PDSO20
封裝: SOIC-20
文件頁(yè)數(shù): 2/4頁(yè)
文件大?。?/td> 43K
代理商: MK1479S
MK1479
Digital 21230 Video Codec Clock
MDS1479GC
2
Revision 2108
Printed 2/10/98
MicroClock division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
Number
Name
Type
Description
1
GND
P
Connect to ground.
2
X2
O
Crystal connection. Connect to a 27.00 MHz fundamental crystal.
3
X1
I
Crystal connection. Connect to a 27.00 MHz fundamental crystal.
4
VDD
P
Connect to +5V.
5
GND
P
Connect to ground.
6
VDD
P
Connect to +5V.
7
GND
P
Connect to ground.
8
16.65M
O
16.65 MHz clock output for AD2181.
9
11.1M
O
11.10 MHz clock output.
10
13.5M
O
13.50 MHz clock output.
11
16.9344M
O
16.9344 MHz clock output for AD1848.
12
24.576M
O
24.576 MHz clock output for AD1848.
13
24.576M
O
24.576 MHz clock output for Philips 7111.
14
GND
P
Connect to ground.
15
VDD
P
Connect to +5V.
16
27M
O
27.00 MHz reference clock output.
17
GND
P
Connect to ground.
18
71.5M
O
71.5 MHz inverted clock output (copy of 71.5 delayed 7ns). Amplitude = VDDP.
19
71.5M
O
71.5 MHz clock output for DEC processor. Amplitude = VDDP.
20
VDDP
P
Connect to +5V or +3.3V. Determines amplitude of 71.5MHz clocks.
1
16
2
3
4
15
14
13
VDD
GND
X2
VDD
GND
5
6
7
8
12
11
10
9
24.576M
NC
X1
GND
VDDP
27M
24.576M
13.5M
11.1M
16.65M
PCS1
PCS0
PCLK (MHz)
0
50.000
0
1
16.667
M
0
test
M
1
32.000
1
0
40.000
1
20.000
18
17
19
20
GND
VDD
16.9344M
GND
MK1479
Processor Clock Select Table
MK1479
UART Clock Select Table
UCS
UCLK (MHz)
0
18.432
1
3.6864
0 = connect directly to ground, 1 = connect directly
to VDD, M = leave floating or unconnected
71.5M
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