參數(shù)資料
型號: MIC9130YQSTR
廠商: MICREL INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 2500 kHz SWITCHING FREQ-MAX, PDSO16
封裝: LEAD FREE, QSOP-16
文件頁數(shù): 4/19頁
文件大?。?/td> 251K
代理商: MIC9130YQSTR
MIC9130
Micrel, Inc.
M9999-111108
12
November 2008
Tt
t
Where t
P_OSCILLATOR
CHARGE
DISCHARGE
DELAY
=+
+
=75ns
f
T
S OSCILLATOR
P OSCILLATOR
_
=
1
ff
S OUTPU
S OSCILLATOR
__
1
4
The timing capacitor, COSC, should be an NPO ceramic or a
temperature stable lm capacitor. Care must be taken when
using capacitor values less than 47pF. The high impedance of
a small value capacitor makes the OSC pin more susceptible
to switching noise. Also, the input capacitance of the OSC pin
and the stray capacitance of the board will have a noticeable
effect on the oscillator frequency.
75ns
1-shot
3V
SYNC
VBIAS
OSC
ROSC
COSC
AGND
VOSC
Gate Drive
(pin 16)
tON
tPERIOD
4
9
5
11
Figure 5a
Higher Switching Frequencies
The MIC9130 is capable of very high switching frequencies.
One of the limitations on the maximum frequency is the cur-
rent capability of the 5V regulator supplying the oscillator
and VBIAS. By powering VBIAS with an external source, e.g.
linear regulator much higher switching frequencies can be
achieved. A simple way of using an external current source
is to set an NPN as an emitter follower. Figure 5b shows the
MIC9130 oscillator frequency set to 4MHz using an external
NPN. The emitter followerj circuit allows the current to be
supplied by VCC while the voltage is regulated to a diode
drop below VBIAS. This conguration is quite stable over
temperature and voltage variations.
75ns
1-shot
3V
SYNC
VBIAS
OSC
ROSC
1.6k
COSC
33pF
AGND
4
9
5
11
VCC 2
1μF
4.7μF
2N3904
Figure 5b
Oscillator Synchronization
The switching frequency of the MIC9130 can be synchronized
to an external oscillator or frequency source. Figure 6 shows
the relationship between the sync input, oscillator waveform
and gate drive output. The external frequency should be set
at least 15% greater than the free running oscillator frequency
to account for tolerances in the oscillator circuit and external
components. The positive edge of the sync signal resets the
oscillator. The sync pulse frequency, like the oscillator, is twice
the gate drive frequency. When an external sync signal is
applied, the peak amplitude of the oscillator signal (pin 4) is
less than when it is free running because the oscillator signal
is terminated before it reaches its 3V (typical) amplitude.
When not used, the sync pin should be connected to ground
to prevent noise from erroneously resetting the oscillator.
TIME (500ns/div)
Sync
Input
(pin
5)
Gate
Drive
(pin
16)
Oscillator W
aveform (pin
4)
Figure 6. Sync Waveform
Soft Start Circuit
The soft start is programmed by a capacitor on the soft start
pin. A 4μA current source charges up the capacitor. At power
up, the SS pin is discharged. Once the UVLO and enable
functions release the soft start circuit, the voltage of the ca-
pacitor increases. The active voltage range of the soft start
pin is from typically from 0.9V to 1.7V. The internal current
source increases the voltage on the soft start capacitor to
approximately 4V. The soft start pin and the current sense
voltage are connected to a comparator in t
PMIC9130. The voltage from the soft start pin effectively
limits the peak current through the current sense resistor by
prematurely terminating the on-time of the gate drive output.
Referring to Figure 1, with the soft start voltage low, the duty
cycle of the output is at a minimum. As the soft start voltage
increases, the duty cycle of the gate drive output increases
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