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參數(shù)資料
| 型號(hào)： | MIC693MC |
| 廠商： | MICREL INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | SOP-16 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | MIC693MC |
MIC691/693
Micrel
MIC691/693
2
July 2000
Pin Configuration
1
2
3
4
5
6
7
8
VBATT
VOUT
VCC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
16
15
14
13
12
11
10
9
RESET
WDO
CE IN
CE OUT
WDI
PFO
PFI
MIC691
MIC693
MIC691NC 16-Lead PDIP Package
MIC691MC 16-Lead SOP Package
MIC693NC 16-Lead PDIP Package
MIC693MC 16-Lead SOP Package
Pin Description
Pin Number
Pin Name
Pin Function
1
VBATT
Backup Battery/auxiliary power input. When V
CCfalls below VBATT, auxiliary
power is routed to V
OUT through a PMOS switch. VBATT pin shoul be
conected to GND if backup battery or auxiliary power is not is not used
2
VOUT
Output for supply voltage. During normal operation (V
CC > VBATT), VCC is
routed to V
OUT through a PMOS switch with a typical on resistance of less
than 1
. The V
OUT pin can source a continous current of up to 250mA.
When V
CC drops below VBATT, auxiliary power is routed from the VBATT pin
to V
OUT through a PMOS switch with a typical on resistance fo less than
15
. Ht e V
OUT pin can source a continous current of up to 25mA when in
battery mode (V
CC < VBATT)
3
VCC
Primary supply voltage, +5V
4
GND
IC ground pin, 0V reference
5
BATT ON
Backup Battery Mode indicater. Logic low during normal operation( V
CC
drops below V
BATT. BATT ON output can typically sink 60mA. This output
can also be used for high current applications which require the V
OUT pin to
source more than 250mA by providing base drive to an external PNP
transistor.
6
/LOWLINE
Low V
CC indicator, goes low when VCC drops below the reset threshold.
7
OSC IN
External Oscillator Input. When OSC SEL is driven low, an external clock or
an external capacitor can be connected to OSC IN to reset the timeout
periods (Table 1.). The internal oscillator is enabled when OSC SEL is
driven high or left floating. When using the internal oscillator, the watchdog
timeout period is set to 00ms by connecting the OSC IN pinto GND or to 1.6
seconds if the OSC IN is left floating. In either case, the watchdog timeout
period following a reset is 1.6 seconds
8
OSC SEL
Oscillator Select Input. An internal oscillator sets the the watchdog timeout
period and reset delay when the OSC SEL is driven high or left floating.
When OSC SEL is driven low, an external clock or capacito on the OSC IN
pin can be used to set the watchdog timeout period and reset delay.
9
PFI
Power fail input. Internally connected to the power fail comparator which is
referenced to 1.25V. The power fail output (/PFO) remains hih if PFI is
above 1.25V. PFI should be connected to GND or VOUT if the power fail
comparator is not used
相關(guān)PDF資料 |
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| MIC9130YQSTR | SWITCHING CONTROLLER, 2500 kHz SWITCHING FREQ-MAX, PDSO16 |
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| MICD-095-06.00-STL-TBL | INTERCONNECTION DEVICE |
| MICD-095-06.00-STR-TBL | INTERCONNECTION DEVICE |
| MICD-095-06.00-TBL-STR | INTERCONNECTION DEVICE |
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