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參數資料
| 型號： | MIC2590B-5BTQ TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 11/23頁 |
| 文件大小： | 230K |
| 描述： | IC PCI HOT PLUG CTLR DUAL 48TQFP |
| 標準包裝： | 2,000 |
| 類型： | 熱交換控制器 |
| 應用： | PCI，PCI-X |
| 內部開關： | 無 |
| 電源電壓： | 3.3V，5V，±12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2590B-5BTQTR MIC2590B-5BTQTR-ND |
Micrel, Inc.
MIC2590B
September 2008
11
M9999-091808
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying
live supply voltages ( hot plugged ), high inrush currents
often result due to the charging of bulk capacitance that
resides across the circuit boards supply pins. This
transient inrush current can cause the systems supply
voltages to temporarily go out of regulation, causing data
loss or system lock-up. In more extreme cases, the
transients occurring during a hot plug event may cause
permanent damage to connectors or on-board
components.
The MIC2590B addresses these issues by limiting the
inrush currents to the load (PCI Board), and thereby
controlling the rate at which the loads circuits turn on. In
addition, the MIC2590B offers input and output voltage
supervisory functions and current-limiting to provide
robust protection for both the host system and the PCI
board.
System Interfaces
The MIC2590B employs two system interfaces. One is the
hot plug Interface (HPI) which includes ON[A/B],
AUXEN[A/B], and /FAULT[A/B]. The other is the System
Management Interface (SMI) consisting of SDA, SCL and
/INT, (whose signals conform to the specifications and
format of Intels SMBus standard). The MIC2590B can be
operated exclusively from the SMI, or can employ the HPI
for power control while continuing to use the SMI for
access to all but the power control registers.
In addition to the basic power control features of the
MIC2590B accessible by the HPI, the SMI also gives the
host access to the following information from the part:
1. Output voltage from each supply.
2. Output current from each supply.
3. Fault conditions occurring on each supply.
When using the System Management Interface for power
control, do not use the hot plug Interface. Conversely,
when using the HPI for power control, do not execute
power control commands over the SMI bus (all other
register accesses via the SMI bus remain permissible
while in the HPI control mode). Note that if power control
is performed via the SMIbus, the AUXENA, AUXENB,
ONA and ONB pins should be tied to ground.
Power-On Reset and Power Cycling
The MIC2590B utilizes V
STBY
as the main supply input
source. It is required for proper operation of the
MIC2590B SMBus, registers and ADC and must be
applied at all times. A Power-On Reset (POR) cycle is
initiated after V
STBY
rises above its UVLO threshold and
remains valid at that voltage for 500祍. All internal
registers except RESULT are cleared after POR. If V
STBY
is recycled the MIC2590B enters a new power-on reset
cycle. V
STBY
must be the first supply input applied.
Following the POR interval, the MAIN supply inputs of
12V
IN
, 12MV
IN
, 5V
IN
and 3V
IN
may be applied in any order.
The SMBus is ready for access at the end of the POR
interval. During t
POR
all outputs are off.
Power-Up Cycle (See Typical Application Circuit)
When a slot is off, the 5V
GATE
and 3V
GATE
pins are held
low with an internal pull-down current source. When a
slots main outputs are enabled, and all input voltages are
above their respective undervoltage lockout thresholds, all
four main supplies execute a controlled turn on. At this
time, the GATE voltages of the 5V and 3.3V MOSFETs
are ramped at a controlled rate from 0V to approximately
11.5V. This is sufficient to fully enhance the external
MOSFETs for lowest possible DC losses. The ramp rate
is controlled by 25礎 (typ.) current sources from the
GATE pins charging each C
GATE
. The magnitude and slew
rate of the output current is proportional to the value of
C
GATE
and the load capacitance. The minimum value of
C
GATE
is selected to ensure that during start-up the load
current does not exceed the current-limit threshold. The
following equation is used to determine the value of C
GATE
(min):
LOAD
LIM
GATE
GATE
C
I
I
(min)
C
?/DIV>
=
Where C
LOAD
is the load capacitance connected to the
3.3V and 5V outputs and I
LIM
and I
GATE
are respectively
the current-limit and gate charge current specifications as
given in the Electrical Characteristics table. The output
slew rate dv/dt is computed by:
6
GATE
GATE
10
C
I
)
dv/dt(load
?/DIV>
=
I
SLEW
= 25礎
C
GATE
dv/dt (load)
0.001礔
25000V/s
0.01礔
2500V/s
0.1礔
250V/s
1礔
25V/s
Table 1. 3.3V/5V Output Slew Rate Selection
For the +12V and 12V supplies, the output slew rate is
controlled by capacitors connected to the 12V
SLEWA
and
12V
SLEWB
pins. To determine the minimum value of the
slew rate capacitor, (C
SLEW
), connected to 12V
SLEW
[A/B],
the following equation is used:
LOAD
LIM
SLEW
SLEW
C
I
I
(min)
C
?/DIV>
=
where C
LOAD
is the load capacitance connected to the
+12V and 12V outputs, and I
LIM
and I
SLEW
are
respectively the current-limit and slew rate charge current
values found in the Electrical Characteristics table. The
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