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參數(shù)資料
| 型號(hào)： | MH89760BS |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 22/38頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | MH89760BS |
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4-76
MH89760B
Preliminary Information
The switch matrix can be built so that the maximum
throughput delay is 1 frame +2 channels. The switch
matrix will not only route data channels to their
destination, but it will also route the received
signalling bits through to the destination channel.
This is necessary because the receiving MH89760B
decodes the T1 stream, and the transmitting
MH89760B has to reconstruct the outgoing T1
stream. In other words, there is no multiframe
integrity between received data and transmitted
data. The total throughput delay is one frame plus
ten ST-BUS channels for the MH89760B receiver,
2.5 ST-BUS channels for the MH89760B transmitter,
and one frame plus two ST-BUS channels for the
switch matrix for a total of 2.5 frames worst case.
The control block only interfaces with the switch
matrix. Besides routing channels and signalling
through to the proper destination, the switch matrix
must also supply the Master Control Words, and
monitor
the Master Status Words for each
MH89760B.
The clock generation block supplies the ST-BUS
clocks and the T1 transmit clocks that are
synchronized to one of the T1 trunks. All of the
extracted 8 kHz outputs are NANDed together before
they are input to PLL #2 of the MT8941.
Phase-locked Loop #2 of the MT8941, will generate
ST-BUS clock signals for the MH89760Bs and the
MT8980s that are synchronized with the chosen T1
line. The E8Ko of all of the other MH89760Bs can be
tristated from the Master Control Word, which allows
the system controller to select any one of 128 T1
lines to act as the synchronization source. By
Figure 15 - Digital Access Cross Connect System (DACS)
AA
AA
AAAA
AAAA
AAAA
DPLL #2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Switch
Matrix
M
I
C
R
O
Control
Matrix
MT8980
MT8980
MT8941
DPLL #1
MH89760B
MH89760B
DSTi
DSTo
T1 Interfaces
Clock
Generator
izer
Equal-
izer
CSTi0
CSTo
CSTi1
C2i
F0i
C1.5i
OUTA
OUTB
RxT
RxR
E8Ko
DSTi
DSTo
CSTi0
CSTo
CSTi1
C2i
F0i
C1.5i
OUTA
OUTB
RxT
RxR
E8Ko
STi7
STo7
STi0
STo0
F0i
C4i
F0i
C4i
STi7
STo7
STi0
STo1
STo2
STo0
F0i
C4i
C2i
C1.5i
CVb
F0i
F0b
C4b
C20
C12i
C16i
C8Kb
12.352
MHz Osc.
MHz Osc.
16.384
Equal-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH89761 | T1 Transmit Equalizer Advance Information |
| MH89770N | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89770 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89770S | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH89761 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1 Transmit Equalizer Advance Information |
| MH89770 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/ESF Framer & Interface Preliminary Information |
| MH89770N | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/ESF Framer & Interface Preliminary Information |
| MH89770S | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/ESF Framer & Interface Preliminary Information |
| MH89790B | 制造商:MITEL 功能描述: 制造商:ZARLNK 功能描述: |
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