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參數(shù)資料
| 型號： | MH16V724AWJ-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM |
| 中文描述： | 快速頁面模式1207959552 -位（16777216 - Word的72 -位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 189K |
| 代理商： | MH16V724AWJ-6 |
MITSUBISHI LSIs
MH16V724AWJ -5, -6
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI
ELECTRIC
( / 20 )
8
26/Feb./1997
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0124-0.0
Read and Refresh Cycles
Limits
Parameter
Symbol
Unit
-6
(Note 21)
(Note 21)
Write Cycle (Early Write and Delayed Write)
10000
10000
0
0
110
60
15
60
15
10
30
15
Min
Max
Limits
Parameter
Symbol
Unit
(Note 23)
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
15
15
0
110
60
15
60
15
10
0
10
15
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
/OE hold time after /W low
-6
Min
Max
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tORH
tOCH
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
/RAS hold time after /OE low
/CAS hold time after /OE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Unit
Min
150
95
Max
-6
(Note22)
(Note23)
(Note23)
(Note23)
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/OE hold time after /W low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
tCWL
tRWL
tWP
tDS
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
50
0
30
75
45
15
15
15
50
95
Note 22:tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS
≥
tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD
≥
tCWD(min), tRWD
≥
tRWD (min), tAWD
≥
tAWD(min) and tCPWD
≥
tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
15
-5
10000
10000
0
0
90
50
15
50
15
10
25
13
13
Min
Max
10000
10000
10
15
15
10
0
90
50
15
50
15
0
10
13
-5
Min
Max
Min
130
85
Max
-5
10000
10000
50
0
30
65
40
10
15
15
10
0
10
50
85
10
0
10
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
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