參數(shù)資料
型號： MH16V724AWJ-6
廠商： Mitsubishi Electric Corporation
英文描述： FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
中文描述： 快速頁面模式1207959552 -位（16777216 - Word的72 -位）動態(tài)隨機存儲器
文件頁數(shù)： 7/20頁
文件大小： 189K
代理商： MH16V724AWJ-6
MITSUBISHI LSIs
MH16V724AWJ -5, -6
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI
ELECTRIC
( / 20 )
7
26/Feb./1997
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0124-0.0
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
SWITCHING CHARACTERISTICS
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD
≥
tRCD(max), tASC
≥
tASC(max) and tCP
≥
tCP(max).
9: Assumes that tRCD
≤
tRCD(max) and tRAD
≤
tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD
≥
tRAD(max) and tASC
≤
tASC(max).
11: Assumes that tCP
≤
tCP(max) and tASC
≥
tASC(max).
12: tOEZ (max) and tOFF(max) defines the time at which the output achieves the high impedance state (IOUT
≤
I ± 10uA I ) and is not reference to
VOH(min) or VOL(max).
Limits
Parameter
Symbol
Unit
- 6
Min
Max
15
60
tCAC
tRAC
tAA
tCPA
tOEA
tCLZ
tOEZ
tOFF
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Access time from /OE
Output low impedance time /CAS low
Output disable time after /OE high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
(Note 12)
ns
ns
ns
ns
ns
ns
ns
ns
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
Min
Max
Parameter
Symbol
Unit
(Note15)
(Note16)
(Note17)
64
45
30
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics are
2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
16: tRAD(max) is specified as a reference point only. If tRAD
≥
tRAD(max) and tASC
≤
tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD
≥
tRCD(max) and tASC
≥
tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
(Note18)
(Note18)
(Note19)
(Note19)
(Note20)
-6
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
0
40
20
10
10
15
0
0
10
15
0
0
15
15
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
35
15
5
10
Output disable time after /CAS high
(Note 12)
15
15
- 5
Min
Max
13
50
25
30
13
5
13
13
50
Min
Max
64
37
25
-5
0
30
18
5
10
13
0
0
8
13
0
0
13
13
1
5
50
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