參數(shù)資料
型號： MFRC53001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 A Reader IC
封裝： MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 5, 2005,;MFRC53001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1
文件頁數(shù)： 113/115頁
文件大?。?/td> 2590K
代理商： MFRC53001T
MFRC530_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 6 July 2010
057433
113 of 115
continued >>
NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
24. Contents
1
2
3
3.1
4
5
6
7
8
8.1
9
9.1
9.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview of supported microprocessor
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic microprocessor interface detection . 7
Connection to different microprocessor types . 8
Separate read and write strobe . . . . . . . . . . . . 8
Common read and write strobe . . . . . . . . . . . . 9
Common read and write strobe: EPP with
handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Peripheral Interface . . . . . . . . . . . . . . . . 9
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory organization of the EEPROM . . . . . . 12
Product information field (read only). . . . . . . . 13
Register initialization files (read/write) . . . . . . 13
StartUp register initialization file (read/write) . 13
Factory default StartUp register initialization
file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register initialization file (read/write) . . . . . . . 15
Crypto1 keys (write only) . . . . . . . . . . . . . . . . 15
Key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Storage of keys in the EEPROM . . . . . . . . . . 16
FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Accessing the FIFO buffer . . . . . . . . . . . . . . . 16
Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Controlling the FIFO buffer. . . . . . . . . . . . . . . 17
FIFO buffer status information . . . . . . . . . . . . 17
FIFO buffer registers and flags. . . . . . . . . . . . 18
Interrupt request system. . . . . . . . . . . . . . . . . 18
Interrupt sources overview . . . . . . . . . . . . . . . 18
Interrupt request handling. . . . . . . . . . . . . . . . 19
Controlling interrupts and getting their status. 19
Accessing the interrupt registers . . . . . . . . . . 19
Configuration of pin IRQ. . . . . . . . . . . . . . . . . 20
Register overview interrupt request system . . 20
9.1.2
9.1.3
9.1.3.1
9.1.3.2
9.1.3.3
9.1.4
9.1.4.1
9.1.4.2
9.2
9.2.1
9.2.2
9.2.2.1
9.2.2.2
9.2.2.3
9.2.3
9.2.3.1
9.2.3.2
9.3
9.3.1
9.3.1.1
9.3.2
9.3.3
9.3.4
9.4
9.4.1
9.4.2
9.4.2.1
9.4.2.2
9.4.3
9.4.4
9.5
9.5.1
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
Timer unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timer unit implementation . . . . . . . . . . . . . . . 21
Timer unit block diagram . . . . . . . . . . . . . . . . 21
Controlling the timer unit . . . . . . . . . . . . . . . . 22
Timer unit clock and period . . . . . . . . . . . . . . 23
Timer unit status. . . . . . . . . . . . . . . . . . . . . . . 23
Using the timer unit functions. . . . . . . . . . . . . 24
Time-out and WatchDog counters . . . . . . . . . 24
Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programmable one shot timer and periodic
trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timer unit registers . . . . . . . . . . . . . . . . . . . . 24
Power reduction modes . . . . . . . . . . . . . . . . . 25
Hard power-down. . . . . . . . . . . . . . . . . . . . . . 25
Soft power-down mode . . . . . . . . . . . . . . . . . 25
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 26
Automatic receiver power-down. . . . . . . . . . . 26
StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 26
Hard power-down phase . . . . . . . . . . . . . . . . 26
Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Initialization phase . . . . . . . . . . . . . . . . . . . . . 27
Initializing the parallel interface type . . . . . . . 27
Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 27
Transmitter pins TX1 and TX2. . . . . . . . . . . . 28
Configuring pins TX1 and TX2. . . . . . . . . . . . 28
Antenna operating distance versus power
consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Antenna driver output source resistance . . . . 29
Source resistance table . . . . . . . . . . . . . . . . . 29
Calculating the relative source resistance . . . 30
Calculating the effective source resistance . . 30
Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Receiver circuit . . . . . . . . . . . . . . . . . . . . . . . 31
Receiver circuit block diagram. . . . . . . . . . . . 31
Receiver operation. . . . . . . . . . . . . . . . . . . . . 31
9.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 32
9.10.2.2 Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 33
9.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 33
9.11
Serial signal switch . . . . . . . . . . . . . . . . . . . . 34
9.11.1
Serial signal switch block diagram. . . . . . . . . 34
9.11.2
Serial signal switch registers . . . . . . . . . . . . . 35
9.11.2.1 Active antenna concept . . . . . . . . . . . . . . . . . 36
9.11.2.2 Driving both RF parts. . . . . . . . . . . . . . . . . . . 37
9.12
MIFARE higher baud rates. . . . . . . . . . . . . . . 37
9.13
MIFARE authentication and Crypto1 . . . . . . . 37
9.13.1
Crypto1 key handling. . . . . . . . . . . . . . . . . . . 38
9.13.2
Authentication procedure. . . . . . . . . . . . . . . . 38
9.5.3
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.8
9.9
9.9.1
9.9.2
9.9.3
9.9.3.1
9.9.3.2
9.9.3.3
9.9.4
9.10
9.10.1
9.10.2
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