參數(shù)資料
型號: MFRC52201HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52201HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 46/92頁
文件大?。?/td> 691K
代理商: MFRC52201HN1
MFRC522_35
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.5 — 21 June 2010
112135
46 of 92
NXP Semiconductors
MFRC522
Contactless reader IC
9.3.2.2
ModeReg register
Defines general mode settings for transmitting and receiving.
Table 55.
Bit
Symbol
Access
Table 56.
Bit
7
9.3.2.3
TxModeReg register
Defines the data rate during transmission.
Table 57.
Bit
Symbol
Access
ModeReg register (address 11h); reset value: 3Fh bit allocation
7
6
5
MSBFirst
reserved
TxWaitRF
R/W
-
R/W
4
3
2
1
0
reserved
-
PolMFin
R/W
reserved
-
CRCPreset[1:0]
R/W
ModeReg register bit descriptions
Symbol
Value
MSBFirst
1
Description
CRC coprocessor calculates the CRC with MSB first
in the CRCResultReg register the values for the
CRCResultMSB[7:0] bits and the CRCResultLSB[7:0] bits are bit
reversed
Remark:
during RF communication this bit is ignored
reserved for future use
transmitter can only be started if an RF field is generated
reserved for future use
defines the polarity of pin MFIN
Remark:
the internal envelope signal is encoded active LOW,
changing this bit generates a MFinActIRq event
polarity of pin MFIN is active HIGH
polarity of pin MFIN is active LOW
reserved for future use
defines the preset value for the CRC coprocessor for the CalcCRC
command
Remark:
during any communication, the preset values are
selected automatically according to the definition of bits in the
RxModeReg and TxModeReg registers
0000h
6363h
A671h
FFFFh
6
5
4
3
reserved
TxWaitRF
reserved
PolMFin
-
1
-
1
0
-
2
1 to 0
reserved
CRCPreset
[1:0]
00
01
10
11
TxModeReg register (address 12h); reset value: 00h bit allocation
7
6
5
TxCRCEn
TxSpeed[2:0]
R/W
D
4
3
2
1
0
InvMod
R/W
reserved
-
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