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| 型號： | MCZ33793EF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSI SLAVE REMOTE SENS 16-SOIC |
| 標準包裝： | 48 |
| 類型： | 傳感器接口 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 并聯(lián) |
| 電流 - 電源： | 250mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 管件 |
| 產品目錄頁面： | 808 (CN2011-ZH PDF) |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33793
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
is reset. The purpose of this is to allow the part to reset itself
if the connection to the master is lost or if power is removed
from the system.
5.0 V REGULATOR
The 5.0 V regulator supplies internal power for the device and
also provides approximately 6.0 mA through the REGOUT
pin to power an external sensor.
UNDERVOLTAGE DETECTOR
The undervoltage detector monitors the output voltage of the
5.0 V regulator. If the REGOUT voltage drops too low for
accurate A/D operation, a signal is sent to the control logic.
The control logic will interpret this signal and, in response to
a command, report a status indicating an undervoltage
condition to have existed. When received, the command will
clear the signal after having read the status. If the voltage is
too low when the A/D conversion was completed, the
returned value will be zero (binary 00000000).
IO PINS 0 TO 3
The IO pins can serve as logic inputs, logic outputs, or analog
inputs. At power-up or after a clear, the pins are all logic
inputs and can be used to measure an analog level value for
an analog value request command. The pins can be
individually configured as logic inputs or outputs by the IO
Control command. If the pin is configured as a logic output,
reading the analog value will return the analog level the
output is being driven to.
ANALOG-TO-DIGITAL CONVERTER
The ADC is an 8-bit successive approximation type using on-
board capacitive division. It uses the Clk signal from the on-
board oscillator for sequencing.
The ADC uses REGOUT as a full-scale reference voltage
and ground AGND for a zero-level reference.
The ADC signals when it has made a valid conversion by
asserting a signal to the controller. If this signal is not
asserted when a value is being captured by the controller, the
controller will signal that an invalid A/D value was obtained.
The value of “0" (binary 00000000) is reserved by the control
logic to signal an error. A value of “0” from the ADC will be
reported as “1” (binary 00000001) by the control logic.
SERIAL ENCODER
The Serial Encoder accepts the digitized value from the ADC
and formatting/data from the Control Logic. A logic transition
from Idle to Signal High and then to Signal Low at BUSIN will
cause the first bit to be presented to the current switch
(Response Loading). A transition to Signal High and back to
Signal Low will cause the next bit to be presented to the
current switch. This will continue until a transition back to Idle
turns off the current switch.
SLEW
The slew circuit serves to reduce EMI produced as a result of
switching the bus loading current sink element. The slew
circuit limits the rise and fall time of current loading the bus by
controlling the current sinking element.
SWITCHED CURRENT SOURCE
A "1" data return bit will be signaled by turning on a fixed
current source. During signaling time, the 33793 will be using
power from H_CAP and not loading the bus for power. The
current will be drawn from either BUSIN or BUSOUT or split
between them. The split can be in any proportion as long as
the total is correct.
The current source is turned off whenever the bus is at Idle
level.
LEVEL DETECTOR
The level detector contains comparators to determine if the
BUSIN or BUSOUT is at idle, logic high, or logic low. The
inputs from BUSIN and BUSOUT are sensed by the device
so that if either side is driven by the signaling waveform while
the other is not, the signaling will be detected. This circuit also
provides a signal to indicate if the signal is being received on
the BUSOUT pin. If a "reverse initialization" command is
received, it can only be acted upon if the device is not already
initialized and if the signal is present on BUSOUT.
SERIAL DECODER
The Serial Decoder monitors transitions on the BUSIN or
BUSOUT. When the 33793 is Idle and supplying power to
itself and the external device(s) (via REGOUT), the input to
BUSIN will be in the Idle state. A transition from this level to
Signal Low (through Signal High) will start the process of
decoding a word of data. BUSIN is driven from Signal Low to
Signal High for each bit and back to Signal Low to start the
next bit. The determination of whether the bit was a one or a
zero is made by determining whether it spent more time low
(a zero) or high (a one). The end of the word is signaled by a
transition at the end of the last bit from Signal High to Idle.
The advantage of this method is that it will accept data over
a wide range of rates and is not dependent on an accurate
clock.
The controller will typically indicate a logic zero by spending
2/3 of the bit period at Signal Low and 1/3 at Signal High. A
logic one would be 1/3 of the bit period at Signal Low and 2/
3 at Signal High.
CONTROL LOGIC
The control logic performs the digital operations carried out
by this device. Its principle functions include:
Decoding input instructions.
Control the general purpose I/O and LOGICOUT in
response to BUSIN or BUSOUT commands.
Control A/D conversions.
Form response word.
Capture and store address.
Control BUSSW.
Reset device on power-up.
Control the general purpose I/O logic configuration.
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