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| 型號(hào)： | MCZ33298EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 8X LOSIDE W/SPI 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
33298
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
DYNAMIC ELECTRICAL CHARACTERISTICS
.
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5V
≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 16V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (VPWR = 13V, RL = 26Ω)
tR
0.4
1.5
20
s
Output Fall Time (VPWR = 13V, RL = 26Ω)
tF
0.4
2.5
20
s
Output Turn ON Delay Time (VPWR = 13V, RL = 26Ω)
tDLY(ON)
1.0
5.0
15
s
tDLY(OFF)
1.0
5.0
15
s
Output Short Fault Disable Report Delay(32)
SFPD = 0.2 x VDD
tDLY(SF)
25
50
100
s
Output OFF Fault Report Delay(33)
SFPD = 0.2 x VDD
tDLY(OFF)
25
50
100
s
DIGITAL INTERFACE TIMING
SCLK Clock Period(34)
tPSCLK
500
—
ns
SCLK Clock High Time
tWSCLKH
175
—
ns
SCLK Clock Low Time
tWSCLKL
175
—
ns
Required Low State Duration for Reset (VIL < 0.2VDD)
tW(RST)
250
50
—
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
250
50
—
ns
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
tLAG
250
50
—
ns
SI to Falling Edge of SCLK (Required for Setup Time)
tSISU
125
25
—
ns
Falling Edge of SCLK to SI (Required for Hold Time)
tSI(HOLD)
125
25
—
ns
SO Rise Time (CL = 200pF)
tRSO
—
25
75
ns
SO Fall Time (CL = 200pF)
tFSO
—
25
75
ns
SI, CS, SCLK, Incoming Signal Rise Time(36)
tRSI
—
200
ns
SI, CS, SCLK, Incoming Signal Fall Time(36)
tFSI
—
200
ns
Time from Falling Edge of CS to SO Low-impedance(37)
tSO(EN)
—
200
ns
Time from Rising Edge of CS to SO High-impedance(38)
tSO(DIS)
—
200
ns
Time from Rising Edge of SCLK to SO Data Valid(39)
0.2VDD < SO > 0.8VDD, CL = 200pF
tVALID
—
50
125
ns
Notes
29.
Output Rise and Fall time respectively measured across a 26
Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.
30.
Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
31.
Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
32.
Output Short Fault Delay time measured from rising edge of CS to IOUT -= 2.0A point with output ON, VOUT = 5.0V, and SFPD = 0.2
VDD. See Figures 8 and 10.
33.
Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9.
34.
Clock period include 75ns rise plus 75ns fall transition in addition to clock high and low time.
35.
RST Low duration measured with outputs enabled and going to OFF or disabled condition.
36.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
37.
Time required for output status data to be available for use at the SO pin.
38.
Time required for output status data to be terminated at the SO pin.
39.
Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5.
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