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參數資料
型號： MCP3304-CI/P
廠商： Microchip Technology
文件頁數： 34/48頁
文件大?。?/td> 0K
描述： IC ADC 13BIT 2.7V 4CH SPI 16-DIP
標準包裝： 30
位數： 13
采樣率（每秒）： 100k
數據接口： 串行，SPI?
轉換器數目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 16-DIP（0.300"，7.62mm）
供應商設備封裝： 16-PDIP
包裝： 管件
輸入數目和類型： 8 個單端，單極；4 個差分，單極
產品目錄頁面： 672 (CN2011-ZH PDF)
其它名稱： MCP3304CI/P
MCP3302/04
DS21697F-page 4
2011 Microchip Technology Inc.
Analog Inputs
Full Scale Input Span
CH0 - CH7
-VREF
—VREF
V
Absolute Input Voltage
CH0 - CH7
-0.3
—
VDD + 0.3
V
Leakage Current
—
0.001
±1
A
Switch Resistance
RS
—1
—
k
Sample Capacitor
CSAMPLE
—
25
—
pF
Digital Input/Output
Data Coding Format
Binary Two’s Complement
High Level Input Voltage
VIH
0.7 VDD
——
V
Low Level Input Voltage
VIL
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
——
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
A
VOUT = VSS or VDD
Pin Capacitance
CIN, COUT
—
10
pF
TA = +25°C, F = 1 MHz, Note 1
Timing Specifications:
Clock Frequency
(Note 8)
FCLK
0.105
—
2.1
MHz
VDD = 5V, FSAMPLE = 100 ksps
Clock High Time
THI
210
—
ns
Clock Low Time
TLO
210
—
ns
CS Fall To First Rising CLK Edge
TSUCS
100
—
ns
Data In Setup time
TSU
50
—
ns
Data In Hold Time
THD
50
—
ns
CLK Fall To Output Data Valid
TDO
——
125
ns
VDD = 5V, see Figure 1-2
—
200
ns
VDD = 2.7V, see Figure 1-2
CLK Fall To Output Enable
TEN
——
125
ns
VDD = 5V, see Figure 1-2
—
200
ns
VDD = 2.7V, see Figure 1-2
CS Rise To Output Disable
TDIS
—
100
ns
See test circuits, Figure 1-2
CS Disable Time
TCSH
475
—
ns
DOUT Rise Time
TR
—
100
ns
See test circuits, Figure 1-2
DOUT Fall Time
TF
—
100
ns
See test circuits, Figure 1-2
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3: VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4.
5: Maximum clock frequency specification must be met.
6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
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