參數(shù)資料
型號： MCP3304-CI/P
廠商： Microchip Technology
文件頁數(shù)： 17/48頁
文件大?。?/td> 0K
描述： IC ADC 13BIT 2.7V 4CH SPI 16-DIP
標準包裝： 30
位數(shù)： 13
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 16-DIP（0.300"，7.62mm）
供應商設備封裝： 16-PDIP
包裝： 管件
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
產(chǎn)品目錄頁面： 672 (CN2011-ZH PDF)
其它名稱： MCP3304CI/P
MCP3302/04
DS21697F-page 24
2011 Microchip Technology Inc.
FIGURE 6-1:
Output Code Transfer Function.
6.2
Communicating with the MCP3302
and MCP3304
Communication with the MCP3302/04 devices is done
using a standard SPI-compatible serial interface.
Initiating communication with either device is done by
bringing the CS line low (see Figure 6-2). If the device
was powered up with the CS pin low, it must be brought
high and back low to initiate communication. The first
clock received with CS low and DIN high will constitute
a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single-
ended or differential input mode. Each channel in
Single-ended mode will operate as a 12-bit converter
with a unipolar output. No negative codes will be output
in Single-ended mode. The next three bits (D0, D1, and
D2) are used to select the input channel configuration.
Table 6-1 and Table 6-2 show the configuration bits for
the MCP3302 and MCP3304, respectively. The device
will begin to sample the analog input on the fourth rising
edge of the clock after the start bit has been received.
The sample period will end on the falling edge of the
fifth clock following the start bit.
After the D0 bit is input, one more clock is required to
complete the sample and hold period (DIN is a “don’t
care” for this clock). On the falling edge of the next
clock, the device will output a low null bit. The next 13
clocks will output the result of the conversion with the
sign bit first, followed by the 12 remaining data bits, as
shown in Figure 6-2. Note that if the device is operating
in the Single-ended mode, the sign bit will always be
transmitted as a ‘0’. Data is always output from the
device on the falling edge of the clock. If all 13 data bits
have been transmitted, and the device continues to
receive clocks while the CS is held low, the device will
output the conversion result, LSB, first, as shown in
Figure 6-3. If more clocks are provided to the device
while CS is still low (after the LSB first data has been
transmitted), the device will clock out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
using the MCP3302/04 devices with hardware SPI
ports.
IN+ > IN-
IN+ < IN-
0 + 0000 0000 0001 (+1)
0 + 0000 0000 0010 (+2)
0 + 0000 0000 0011 (+3)
1 + 1111 1111 1101 (-3)
1 + 1111 1111 1110 (-2)
1 + 1111 1111 1111 (-1)
0 + 1111 1111 1110 (+4094)
0 + 1111 1111 1111 (+4095)
1 + 0000 0000 0000 (-4096)
1 + 0000 0000 0001 (-4095)
Output
Code
0 + 0000 0000 0000 (0)
VREF
-VREF
Positive Full
Scale Output = VREF -1 LSB
Negative Full
Scale Output = -VREF
Analog Input
IN+ - IN-
Voltage
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