400h(2) INDF0 Addr" />
參數(shù)資料
型號： MCP2150T-I/SO
廠商： Microchip Technology
文件頁數(shù)： 44/52頁
文件大小： 0K
描述： IC IRDA STD CONTROLLER 18SOIC
標準包裝： 1,100
控制器類型： IRDA 標準協(xié)議?？刂破?br>
接口： UART
電源電壓： 3 V ~ 5.5 V
電流 - 電源： 7mA
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 18-SOIC
包裝： 帶卷 (TR)
配用： MCP215XDM-ND - BOARD DEMO FOR MCP215X
其它名稱： MCP2150TI/SO
2009 Microchip Technology Inc.
Preliminary
DS41364D-page 49
PIC16F193X/LF193X
Bank 8
400h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
401h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
402h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
403h(2)
STATUS
—
—TO
PD
ZDC
C
---1 1000 ---q quuu
404h(2)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
405h(2)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
406h(2)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
407h(2)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
408h(2)
BSR
—
BSR<4:0>
---0 0000 ---0 0000
409h(2)
WREG
Working Register
0000 0000 uuuu uuuu
40Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
40Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
40Ch
—
Unimplemented
—
40Dh
—
Unimplemented
—
40Eh
—
Unimplemented
—
40Fh
—
Unimplemented
—
410h
—
Unimplemented
—
411h
—
Unimplemented
—
412h
—
Unimplemented
—
413h
—
Unimplemented
—
414h
—
Unimplemented
—
415h
TMR4
Timer 4 Module Register
0000 0000 0000 0000
416h
PR4
Timer 4 Period Register
1111 1111 1111 1111
417h
T4CON
—
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
-000 0000 -000 0000
418h
—
Unimplemented
—
419h
—
Unimplemented
—
41Ah
—
Unimplemented
—
41Bh
—
Unimplemented
—
41Ch
TMR6
Timer 6 Module Register
0000 0000 0000 0000
41Dh
PR6
Timer 6 Period Register
1111 1111 1111 1111
41Eh
T6CON
—
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
-000 0000 -000 0000
41Fh
—
Unimplemented
—
TABLE 3-14:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
4:
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
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