參數(shù)資料
型號(hào): MCIMX357DJQ5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 144/147頁
文件大?。?/td> 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
96
4.9.15
MediaLB Controller Electrical Specifications
This section describes the electrical information of the MediaLB Controller module.
MSHC_DATA
Setup time
tDsu
5
ns
Hold time
tDh
5
ns
Output delay time
tDd
15
ns
1 Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC
restrictions described in Table 61.
Table 61. Parallel Interface Timing Parameters1
1 Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC
restrictions described in Table 8.
Signal
Parameter
Symbol
Standards
Unit
Min.
Max.
MSHC_SCLK
Cycle
tSCLKc
25
ns
H pulse length
tSCLKwh
5
ns
L pulse length
tSCLKwl
5
ns
Rise time
tSCLKr
10
ns
Fall time
tSCLKf
10
ns
MSHC_BS
Setup time
tBSsu
8
ns
Hold time
tBSh
1
ns
MSHC_DATA
Setup time
tDsu
8
ns
Hold time
tDh
1
ns
Output delay time
tDd
15
ns
Table 62. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK operating frequency1
fmck
11.264
12.288
24.576
24.6272
25.600
MHz
Min: 256
× Fs at 44.0 kHz
Typ: 256
× Fs at 48.0 kHz
Typ: 512
× Fs at 48.0 kHz
Max: 512
× Fs at 48.1 kHz
Max: 512
× Fs PLL unlocked
MLBCLK rise time
tmckr
——
3
ns
VIL TO VIH
Table 60. Serial Interface Timing Parameters1 (continued)
Signal
Parameter
Symbol
Standards
Unit
Min.
Max.
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