參數資料
型號: MCIMX357DJQ5CR2
廠商: Freescale Semiconductor
文件頁數: 12/147頁
文件大?。?/td> 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標準包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數: 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
109
4.9.18
Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
Figure 85. USB Transmit/Receive Waveform in Parallel Mode
4.9.19
PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
Table 74. Signal Definitions—Parallel Interface
Name
Direction
Signal Description
USB_Clk
In
Interface clock. All interface signals are synchronous to the clock.
USB_Data[7:0]
I/O
Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.
USB_Dir
In
Direction. Control the direction of the data bus.
USB_Stp
Out
Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.
USB_Nxt
In
Next. The PHY asserts this signal to throttle the data.
Table 75. USB Timing Specification in VP_VM Unidirectional Mode
ID
Parameter
Min.
Max.
Unit
Conditions /
Reference Signal
US15
USB_TXOE_B
6.0
ns
10 pF
US16
USB_DAT_VP
0.0
ns
10 pF
US17
USB_SE0_VM
9.0
ns
10 pF
USB_Dir/Nxt
USB_Stp
US17
US16
USB_Data
US15
US16
US15
US17
USB_Clk
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