參數(shù)資料
型號： MCIMX31VMN5CR2
廠商： Freescale Semiconductor
文件頁數(shù)： 105/122頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31L 473-MAPBGA
標準包裝： 750
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 473-LFBGA
包裝： 帶卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
83
IP56 Controls setup time for write
Tdcsw
Tdicuw–1.5
Tdicuw
—
ns
IP57 Controls hold time for write
Tdchw
Tdicpw–Tdicdw–1.5
Tdicpw–Tdicdw
—
ns
IP58 Slave device data delay8
Tracc
0
—
Tdrp9–Tlbd10–Tdicur–1.5
ns
IP59 Slave device data hold time8
Troh
Tdrp–Tlbd–Tdicdr+1.5
—
Tdicpr–Tdicdr–1.5
ns
IP60 Write data setup time
Tds
Tdicdw–1.5
Tdicdw
—
ns
IP61 Write data hold time
Tdh
Tdicpw–Tdicdw–1.5
Tdicpw–Tdicdw
—
ns
IP62 Read period2
Tdicpr
Tdicpr–1.5
Tdicpr
Tdicpr+1.5
ns
IP63 Write period3
Tdicpw
Tdicpw–1.5
Tdicpw
Tdicpw+1.5
ns
IP64 Read down time4
Tdicdr
Tdicdr–1.5
Tdicdr
Tdicdr+1.5
ns
IP65 Read up time5
Tdicur
Tdicur–1.5
Tdicur
Tdicur+1.5
ns
IP66 Write down time6
Tdicdw
Tdicdw–1.5
Tdicdw
Tdicdw+1.5
ns
IP67 Write up time7
Tdicuw
Tdicuw–1.5
Tdicuw
Tdicuw+1.5
ns
IP68 Read time point9
Tdrp
Tdrp–1.5
Tdrp
Tdrp+1.5
ns
1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
2 Display interface clock period value for read:
3 Display interface clock period value for write:
4 Display interface clock down time for read:
5 Display interface clock up time for read:
6 Display interface clock down time for write:
7 Display interface clock up time for write:
8 This parameter is a requirement to the display connected to the IPU.
9 Data read point:
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
Table 51. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
ID
Parameter
Symbol
Min.
Typ.1
Max.
Units
Tdicpr
T
HSP_CLK
ceil
DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
=
Tdicpw
T
HSP_CLK
ceil
DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
=
Tdicdr
1
2
--- T
HSP_CLK
ceil
2 DISP#_IF_CLK_DOWN_RD
HSP_CLK_PERIOD
-------------------------------------------------------------------------------
=
Tdicur
1
2
---T
HSP_CLK
ceil
2 DISP#_IF_CLK_UP_RD
HSP_CLK_PERIOD
--------------------------------------------------------------------
=
Tdicdw
1
2
--- T
HSP_CLK
ceil
2 DISP#_IF_CLK_DOWN_WR
HSP_CLK_PERIOD
---------------------------------------------------------------------------------
=
Tdicuw
1
2
---T
HSP_CLK
ceil
2 DISP#_IF_CLK_UP_WR
HSP_CLK_PERIOD
----------------------------------------------------------------------
=
Tdrp
T
HSP_CLK
ceil
DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
=
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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