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| 型號： | MCIMX31LCJMN4D |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA473 |
| 封裝： | 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-473 |
| 文件頁數(shù)： | 67/108頁 |
| 文件大?。?/td> | 2878K |
| 代理商： | MCIMX31LCJMN4D |
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Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
61
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical
4.3.15.5
Asynchronous Interfaces
4.3.15.5.1
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal
(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system
68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when
transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD
signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during
the whole burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 51,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX31CVMN4D,
MCIMX31LCVMN4D,
MCIMX31CVMN4C,
MCIMX31LCVMN4C
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| MCIMX31LCVKN5C | 功能描述:IC MPU MAP I.MX31L 457-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX31 標(biāo)準(zhǔn)包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT |
| MCIMX31LCVKN5CR2 | 功能描述:IC MPU MAP I.MX31L 457-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX31 標(biāo)準(zhǔn)包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT |
| MCIMX31LCVKN5D | 功能描述:處理器 - 專門應(yīng)用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX31LCVKN5DR2 | 功能描述:處理器 - 專門應(yīng)用 2.0.1 CONSUMER LITE RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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