參數(shù)資料
型號： MCIMX31LCJMN4D
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA473
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-473
文件頁數(shù)： 24/108頁
文件大?。?/td> 2878K
代理商： MCIMX31LCJMN4D
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
22
Freescale Semiconductor
Electrical Characteristics
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 21 shows ATA
timing parameters.
Table 21. ATA Timing Parameters
Name
Description
Value/
Contributing Factor1
T
Bus clock period (ipg_clk_ata)
peripheral clock
frequency
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
ti_dh
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H to L
2.5 ns
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
7ns
tskew2
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
transceiver
tskew3
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
transceiver
tbuf
Max buffer propagation delay
transceiver
tcable1
Cable propagation delay for ata_data
cable
tcable2
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
cable
tskew4
Max difference in cable propagation delay between ata_iordy and ata_data (read)
cable
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCIMX31CVMN4D,
MCIMX31LCVMN4D,
MCIMX31CVMN4C,
MCIMX31LCVMN4C
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