
Revision History
MC68HC812A4 Data Sheet, Rev. 7
4
Freescale Semiconductor
August,
2001
(Continued)
4
12.11.3 Data Direction Register for Timer Port
— Repetitive information
removed. See
12.11.2 Timer Port Data Direction Register
18.12 Control Timing
— Minimum values added for PW
IRQ
and PW
TIM
18.14 Non-Multiplexed Expansion Bus Timing
— Table heading changed to
reflect minimum and maximum values at 8 MHz
Table 12-3. Prescaler Selection
— Added value column and updated prescale
factors
18.11 EEPROM Characteristics
— Corrected minimum and maximum values
for programming and erase times
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic
— On sheet
1 of this schematic removed reference to resistor R2
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic
— On
sheet 1 of this schematic removed reference to resistor R2
4.6.2 External Reset
— Corrected reference to eight E-clock cycles to nine
E-clock cycles
209
329
334
September,
2001
5
197
328
August,
2002
6
40
42
77
May,
2006
7
Updated to meet Freescale identity guidelines.
Throughout
1.3 Ordering Information
— Updated
Table 1-1. Ordering Information
and
added
Figure 1-1. Device Numbering System
.
18
Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
24
Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
26
Figure 3-9. Condition Code Register (CCR)
— Corrected reset state for bit 7.
46
Table 4-1. Interrupt Vector Map
— Corrected reference to clock monitor reset.
50
4.5 Resets
— Reworked paragraph for clarity.
52
Figure 5-1. Mode Register (MODE)
— Changed reset state designator from
Peripheral to Special peripheral.
58
Figure 10-3. Clock Function Register Map
— Removed reference to Special
Reset for the COP Control Register.
102
Figure 10-9. COP Control Register (COPCTL)
— Corrected reset states.
107
12.4.1 Prescaler
— Corrected number of prescaler divides.
122
Figure 12-17. Timer Mask 2 Register (TMSK2)
— Corrected reset state for bit 4.
131
Table 16-5. ATD Interrupt Sources
— Corrected table title.
207
18.2 Functional Operating Range
— Corrected operating temperature range
entries.
222
18.10 EEPROM Characteristics
— Corrected minimum value for minimum
programming clock frequency.
226
18.11 Control Timing
— Corrected maximum value for frequency of operation.
227
18.12 Peripheral Port Timing
— Corrected table heading.
231
19.2 Package Dimensions
— Replaced package dimension drawing with the
latest available.
237
Revision History
Date
Revision
Level
Description
Page
Number(s)