參數(shù)資料
型號(hào)： MCF5471ZP200
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁(yè)數(shù)： 27/96頁(yè)
文件大小： 2003K
代理商： MCF5471ZP200
MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
33
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Description
1.5.1.3.10 System Error (PCISERR)
The PCISERR signal, if enabled, is asserted when an address phase parity error is detected.
1.5.1.3.11 Stop (PCISTOP)
The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the current
transaction.
1.5.1.3.12 Target Ready (PCITRDY)
The PCITRDY signal is asserted by the currently addressed target to indicate that it is ready to complete the
current data phase.
1.5.1.3.13 External Bus Grant (PCIBG[4:1])
The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI arbiter
is enabled, it asserts one of the PCIBG[4:1] lines to grant ownership of the PCI bus to an external master.
When the PCI arbiter module is disabled, PCIBG[4:1] are driven high and should be ignored.
1.5.1.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI
arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the MCF547x
needs to initiate a PCI transaction.
1.5.1.3.15 External Bus Request (PCIBR[4:0])
The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.
1.5.1.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)
The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus. When
the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus, PCIGNTIN.
It is driven by an external PCI arbiter.
1.5.1.4
Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF547x device.
1.5.1.4.1
Interrupt Request (IRQ[7:1])
The IRQ[7:1] signals are the external interrupt inputs.
1.5.1.5
Clock and Reset Signals
The clock and reset signals configure the MCF547x and provide interface signals to the external system.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF5472 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics
MCF5472EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire Microprocessor
MCF5472VR200 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5472ZP200 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5473 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics
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