參數(shù)資料
型號(hào)： MCF54455VR266
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA360
封裝： 23 X 23 MM, ROHS COMPLIANT, TEPBGA-360
文件頁(yè)數(shù)： 18/48頁(yè)
文件大?。?/td> 945K
代理商： MCF54455VR266
Electrical Characteristics
MCF5445x ColdFire Microprocessor Data Sheet, Rev. 6
Freescale Semiconductor
25
5.8
SDRAM AC Timing Characteristics
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing
numbers are relative to the four DQS byte lanes.
Table 13. SDRAM Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
60
133.33
MHz
1
1 The SDRAM interface operates at the same frequency as the internal system bus.
DD1
Clock Period
tSDCK
7.5
16.67
ns
DD2
Pulse Width High
tSDCKH
0.45
0.55
tSDCK
2
2 Pulse width high plus pulse width low cannot exceed min and max clock period.
DD3
Pulse Width Low
tSDCKL
0.45
0.55
tSDCK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Valid
tCMV
—
(0.5 x tSDCK)
+ 1.0ns
ns
3
3 Command output valid should be 1/2 the memory bus clock (t
SDCK) plus some minor adjustments for process, temperature, and
voltage variations.
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] — Output Hold
tCMH
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tDQSS
(1.0 x tSDCK)
- 0.6ns
(1.0 x tSDCK)
+ 0.6ns
ns
DD7
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
tQS
1.0
—
ns
4
5
4 This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
5 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
DD8
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tQH
1.0
—
ns
6
6 This specification relates to the required hold time of DDR memories.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
DD9
Input Data Skew Relative to DQS (Input Setup)
tIS
—1.0
ns
7
7 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
DD10 Input Data Hold Relative to DQS.
tIH
(0.25 x tSDCK)
+ 0.5ns
—ns
8
8 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
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