參數資料
型號: MCF5407FT220
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁數: 8/35頁
文件大?。?/td> 441K
代理商: MCF5407FT220
16
MCF5407 Integrated ColdFire Microprocessor Product Brief
MOTOROLA
Programming Model, Addressing Modes, and Instruction Set
Miscellaneous Operands
#<data>
Immediate data following the 16-bit operation word of the instruction
<ea>
Effective address
<ea>y,<ea>x
Source and destination effective addresses, respectively
<label>
Assembly language program label
<list>
List of registers for MOVEM instruction (example: D3–D0)
<shift>
Shift operation: shift left (<<), shift right (>>)
<size>
Operand data size: byte (B), word (W), longword (L)
bc
Both instruction and data caches
dc
Data cache
ic
Instruction cache
# <vector>
Identifies the 4-bit vector number for trap instructions
<>
identifies an indirect data address referencing memory
<xxx>
identifies an absolute address referencing memory
dn
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+
Arithmetic addition or postincrement indicator
Arithmetic subtraction or predecrement indicator
x
Arithmetic multiplication
/
Arithmetic division
~
Invert; operand is logically complemented
&Logical AND
|Logical OR
^
Logical exclusive OR
<<
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
Source operand is moved to destination operand
←→
Two operands are exchanged
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition>
then <operations>
else <operations>
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
Table 4. Notational Conventions (continued)
Instruction
Operand Syntax
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