參數(shù)資料
型號(hào)： MCF5407FT220
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 220 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁(yè)數(shù)： 3/35頁(yè)
文件大?。?/td> 441K
代理商： MCF5407FT220
MOTOROLA
MCF5407 Integrated ColdFire Microprocessor Product Brief
11
ColdFire Module Description
1.3.8.3
16-Bit Parallel Port Interface
A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin
basis.
1.3.8.4
Interrupt Controller
The interrupt controller provides user-programmable control of ten internal peripheral interrupts and
implements four external fixed interrupt-request pins. Each internal interrupt can be programmed to any one
of seven interrupt levels and four priority levels within each of these levels. Additionally, the external
interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. Autovector capability is
available for both internal and external interrupts.
1.3.8.5
JTAG
To help with system diagnostics and manufacturing testing, the MCF5407 processor includes dedicated
user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often
referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a
standard.
1.3.9
System Debug Interface
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators. The debug unit contained in the MCF5407 is a compatible
upgrade to the MCF52xx and MCF53xx debug modules with added breakpoint registers and support for I/O
interrupt request servicing while in emulator mode.
The on-chip breakpoint resources include a total of 13 programmable registers—two sets of address
registers (each with two 32-bit registers), two sets of data registers (each with a 32-bit data register plus
32-bit data mask register), one 32-bit PC register plus a 32-bit PC mask register and three additional 32-bit
PC registers. These registers can be accessed through the dedicated debug serial communication channel,
or from the processor's supervisor mode programming model. The breakpoint registers can be configured
to generate triggers by combining the address, data and PC conditions in a variety of single or dual-level
definitions and the trigger event can be programmed to generate a processor halt, or initiate a debug interrupt
exception.
The MCF5407’s new interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the Version 4 debug module has combined the processor status and debug data
outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus along with the PSTCLK output provide
execution status, captured operand data and branch target addresses defining processor activity at one-half
the CPU's clock rate.
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