參數(shù)資料
型號(hào): MCF5407FT162
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 0.50 MM PITCH, PLASTIC, FQFP-208
文件頁(yè)數(shù): 22/35頁(yè)
文件大?。?/td> 441K
代理商: MCF5407FT162
MCF5407 Product Summary Page
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Semiconductors
MCF5407 : Integrated ColdFire Version 4 Microprocessor
The MCF5407 is the first standard product to implement the Version 4 ColdFire microprocessor core. The
V4 microarchitecture implements a number of advanced techniques, including a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar support (dual-instruction issue),
which contribute to the 316 (Dhrystone 2.1) MIPS performance level. Increasing the internal speed of the
core also allows higher performance while providing the system designer with an easy-to-use lower speed
system interface. The processor complex frequency is an integer multiple, 3 to 6 times, of the external bus
frequency. The core clock can be stopped to support a low-power mode in the MCF5407.
Serial communication channels are provided by two programmable full-duplex UARTs, one of which
provides synchronous communications for soft-modem applications, and an I2C interface module. Four
channels of DMA allow for fast data transfer using a programmable burst mode independent of processor
execution. The two 16-bit general-purpose multimode timers provide separate input and output signals.
For system protection, the processor includes a programmable 16-bit software watchdog timer. In addition,
common system functions such as chip selects, interrupt control, bus arbitration, and an IEEE 1149.1
JTAG module are included.
MCF5407 Features
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V4 ColdFire processor core with Harvard memory architecture and branch cache acceleration
logic
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Limited superscalar design
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Fully code compatible with Version 2 & 3 ColdFire processor core
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Enhanced instruction set
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16K instruction-cache, 8K data-cache
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4KB SRAM
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Multiply Accumulate (MAC) with integer and fractional capabilities
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Industry leading debug module offering both background and real time capability
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Hardware integer divide unit
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Integrated processor
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DRAM controller: glueless interface to SDRAM, FPM and EDO
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1 UART, 1 synchronous UART
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Four fully programmable DMA Channels
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Eight chip selects
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16-bit general purpose I/O
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Two 16-bit timers
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I2C module
r
System Integration (PLL, Software watchdog)
q
Doze mode and variable frequency operation
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MCF5407 Parametrics
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