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DMA Timers (DTIM0–DTIM3)
MCF5271 Reference Manual, Rev. 2
22-6
Freescale Semiconductor
22.2.8 DMA Timer Event Registers (DTERn)
DTERn, shown in Figure 22-4, reports capture or reference events by setting DTERn[CAP] or
DTERn[REF]. This reporting is done regardless of the corresponding DMA request or interrupt
enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to either DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value);
both bits can be cleared at the same time. If configured to generate an interrupt request, the REF
and CAP bits must be cleared early in the interrupt service routine so the timer module can negate
the interrupt request signal to the interrupt controller. If configured to generate a DMA request, the
processing of the DMA data transfer automatically clears both the REF and CAP flags via the
internal DMA ACK signal.
6–1
—
Reserved, should be cleared.
0
MODE16
Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper
bits of the 32-bit timer in diagnostic software without requiring the timer to count through
its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits.
All 32 bits of the counter are still compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
76
54
32
10
R
0
00
000
REF
CAP
W
w1c
Reset
0
00
000
00
Address
IPSBAR + 0x00_0403 (DTER0); IPSBAR + 0x00_0443 (DTER1);
IPSBAR + 0x00_0483 (DTER2); IPSBAR + 0x00_04C3 (DTER3)
Figure 22-4. DMA Timer Event Registers (DTERn)
Table 22-3.
DTXMRn Field Descriptions (Continued)
Bits
Name
Description