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參數(shù)資料
| 型號： | MCF5232 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Microprocessor Hardware Specification |
| 中文描述： | 集成的微處理器，硬件規(guī)格 |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 1462K |
| 代理商： | MCF5232 |
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
50
Figure 18
shows timing for the values in
Table 35
and
Table 36
.
Figure 18. I
2
C Input/Output Timings
6.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
6.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and
ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.
Table 37
lists MII receive channel timings.
I7
1
Data setup time
2
—
t
cyc
I8
1
Start condition setup time (for repeated start
condition only)
20
—
t
cyc
I9
1
Stop condition setup time
10
—
t
cyc
NOTES:
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR
programmed with the maximum frequency (IFDR = 0x20) results in minimum output
timings as shown in
Table 36
. The I
2
C interface is designed to scale the actual data
transition time to move it to the middle of the I2C_SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the
numbers given in
Table 36
are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can
only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on
external signal capacitance and pull-up resistor values.
3
Specified at a nominal 50-pF load.
Table 36. I
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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| MCF5232160QFP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
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| MCF5232CAB80 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM100 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM100 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
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